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	Author	Verreck, D.; Verhulst, A.S.; Van de Put, M.L.; Sorée, B.; Magnus, W.; Collaert, N.; Mocuta, A.; Groeseneken, G.
	Title	Self-consistent procedure including envelope function normalization for full-zone Schrodinger-Poisson problems with transmitting boundary conditions			Type	A1 Journal article
	Year	2018	Publication	Journal of applied physics	Abbreviated Journal	J Appl Phys
	Volume	124	Issue	20	Pages	204501
	Keywords	A1 Journal article; Condensed Matter Theory (CMT)
	Abstract	In the quantum mechanical simulation of exploratory semiconductor devices, continuum methods based on a k.p/envelope function model have the potential to significantly reduce the computational burden compared to prevalent atomistic methods. However, full-zone k.p/envelope function simulation approaches are scarce and existing implementations are not self-consistent with the calculation of the electrostatic potential due to the lack of a stable procedure and a proper normalization of the multi-band envelope functions. Here, we therefore present a self-consistent procedure based on a full-zone spectral k.p/envelope function band structure model. First, we develop a proper normalization for the multi-band envelope functions in the presence of transmitting boundary conditions. This enables the calculation of the free carrier densities. Next, we construct a procedure to obtain self-consistency of the carrier densities with the electrostatic potential. This procedure is stabilized with an adaptive scheme that relies on the solution of Poisson's equation in the Gummel form, combined with successive underrelaxation. Finally, we apply our procedure to homostructure In0.53Ga0.47As tunnel field-effect transistors (TFETs) and staggered heterostructure GaAs0.5Sb0.5/In0.53Ga0.47As TFETs and show the importance of self-consistency on the device predictions for scaled dimensions. Published by AIP Publishing.
	Address
	Corporate Author				Thesis
	Publisher		Place of Publication		Editor
	Language		Wos	000451743900015	Publication Date	2018-11-30
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0021-8979; 1089-7550	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	2.068	Times cited	1	Open Access
	Notes	; This work was supported by imec's Industrial Affiliation Program. ;			Approved	Most recent IF: 2.068
	Call Number	UA @ admin @ c:irua:156291			Serial	5228
Permanent link to this record



	Author	Dabral, A.; Pourtois, G.; Sankaran, K.; Magnus, W.; Yu, H.; de de Meux, A.J.; Lu, A.K.A.; Clima, S.; Stokbro, K.; Schaekers, M.; Collaert, N.; Horiguchi, N.; Houssa, M.
	Title	Study of the intrinsic limitations of the contact resistance of metal/semiconductor interfaces through atomistic simulations			Type	A1 Journal article
	Year	2018	Publication	ECS journal of solid state science and technology	Abbreviated Journal	Ecs J Solid State Sc
	Volume	7	Issue	6	Pages	N73-N80
	Keywords	A1 Journal article; Condensed Matter Theory (CMT); Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
	Abstract	In this contribution, we report a fundamental study of the factors that set the contact resistivity between metals and highly doped n-type 2D and 3D semiconductors. We investigate the case of n-type doped Si contacted with amorphous TiSi combining first principles calculations with Non-Equilibrium Green functions transport simulations. The evolution of the intrinsic contact resistivity with the doping concentration is found to saturate at similar to 2 x 10(-10) Omega.cm(2) for the case of TiSi and imposes an intrinsic limit to the ultimate contact resistance achievable for n-doped Silamorphous-TiSi (aTiSi). The limit arises from the intrinsic properties of the semiconductors and of the metals such as their electron effective masses and Fermi energies. We illustrate that, in this regime, contacting heavy electron effective mass metals with semiconductor helps reducing the interface intrinsic contact resistivity. This observation seems to hold true regardless of the 3D character of the semiconductor, as illustrated for the case of three 2D semiconducting materials, namely MoS2, ZrS2 and HfS2. (C) The Author(s) 2018. Published by ECS.
	Address
	Corporate Author				Thesis
	Publisher	Electrochemical society	Place of Publication	Pennington (N.J.)	Editor
	Language		Wos	000440836000004	Publication Date	2018-05-25
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	2162-8769; 2162-8777	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	1.787	Times cited	2	Open Access	Not_Open_Access
	Notes	; The authors thank the imec core CMOS program members, the European Commission, its TAKEMI5 ECSEL research project and the local authorities for their support. ;			Approved	Most recent IF: 1.787
	Call Number	UA @ lucian @ c:irua:153205UA @ admin @ c:irua:153205			Serial	5130
Permanent link to this record



	Author	Loo, R.; Arimura, H.; Cott, D.; Witters, L.; Pourtois, G.; Schulze, A.; Douhard, B.; Vanherle, W.; Eneman, G.; Richard, O.; Favia, P.; Mitard, J.; Mocuta, D.; Langer, R.; Collaert, N.
	Title	Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures			Type	A1 Journal article
	Year	2018	Publication	ECS journal of solid state science and technology	Abbreviated Journal	Ecs J Solid State Sc
	Volume	7	Issue	2	Pages	P66-P72
	Keywords	A1 Journal article; Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
	Abstract	Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET and Gate All Around devices. We use Si4H10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 degrees. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions. (C) The Author(s) 2018. Published by ECS.
	Address
	Corporate Author				Thesis
	Publisher	Electrochemical society	Place of Publication	Pennington (N.J.)	Editor
	Language		Wos	000425215200010	Publication Date	2018-01-21
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	2162-8769; 2162-8777	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	1.787	Times cited	5	Open Access	OpenAccess
	Notes				Approved	Most recent IF: 1.787
	Call Number	UA @ lucian @ c:irua:149326			Serial	4933
Permanent link to this record



	Author	Yu, H.; Schaekers, M.; Chew, S.A.; Eyeraert, J.-L.; Dabral, A.; Pourtois, G.; Horiguchi, N.; Mocuta, D.; Collaert, N.; De Meyer, K.
	Title	Titanium (germano-)silicides featuring 10^-9 Ω.cm² contact resistivity and improved compatibility to advanced CMOS technology			Type	P1 Proceeding
	Year	2018	Publication	2018 18th International Workshop On Junction Technology (iwjt)	Abbreviated Journal
	Volume		Issue		Pages	80-84 T2 - 18th International Workshop on Junction
	Keywords	P1 Proceeding; Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
	Abstract	uIn this work, we discuss three novel Ti (germano-)silicidation techniques featuring respectively the pre-contact amorphization implantation (PCAI), the TiSi co-deposition, and Ti atomic layer deposition (ALD). All three techniques form TiSix(Ge-y) contacts with ultralow contact resistivity (rho(c)) of (1-3)x10(-9) Omega.cm(2) on both highly doped n-Si and p-SiGe substrates: these techniques meet rho(c) requirement of 5-14 nm CMOS technology and feature unified CMOS contact solutions. We further discuss the compatibility of these techniques to the realistic CMOS transistor fabrication.
	Address
	Corporate Author				Thesis
	Publisher		Place of Publication		Editor
	Language		Wos	000502768600020	Publication Date
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	978-1-5386-4511-6; 978-1-5386-4511-6	ISBN		Additional Links	UA library record; WoS full record
	Impact Factor		Times cited		Open Access
	Notes				Approved	no
	Call Number	UA @ admin @ c:irua:165190			Serial	8673
Permanent link to this record



	Author	Pourtois, G.; Dabral, A.; Sankaran, K.; Magnus, W.; Yu, H.; de de Meux, A.J.; Lu, A.K.A.; Clima, S.; Stokbro, K.; Schaekers, M.; Houssa, M.; Collaert, N.; Horiguchi, N.
	Title	Probing the intrinsic limitations of the contact resistance of metal/semiconductor interfaces through atomistic simulations			Type	P1 Proceeding
	Year	2017	Publication	Semiconductors, Dielectrics, And Metals For Nanoelectronics 15: In Memory Of Samares Kar	Abbreviated Journal
	Volume		Issue		Pages	303-311
	Keywords	P1 Proceeding; Engineering sciences. Technology; Condensed Matter Theory (CMT); Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
	Abstract	In this contribution, we report a fundamental study of the factors that set the contact resistivity between metals and highly doped semiconductors. We investigate the case of n-type doped Si contacted with amorphous TiSi combining first-principles calculations with Non-Equilibrium Green functions transport simulations. The intrinsic contact resistivity is found to saturate at similar to 2x10(-10) Omega.cm(2) with the doping concentration and sets an intrinsic limit to the ultimate contact resistance achievable for n-doped Si vertical bar amorphous-TiSi. This limit arises from the intrinsic properties of the semiconductor and of the metal such as their electron effective masses and Fermi energies. We illustrate that, in this regime, contacting metals with a heavy electron effective mass helps reducing the interface intrinsic contact resistivity.
	Address
	Corporate Author				Thesis
	Publisher	Electrochemical soc inc	Place of Publication	Pennington	Editor
	Language		Wos	000426271800028	Publication Date	2017-10-17
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume	80	Series Issue	1	Edition
	ISSN	978-1-62332-470-4; 978-1-60768-818-1	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor		Times cited	1	Open Access	Not_Open_Access
	Notes	; ;			Approved	Most recent IF: NA
	Call Number	UA @ lucian @ c:irua:149966			Serial	4976
Permanent link to this record



	Author	Loo, R.; Arimura, H.; Cott, D.; Witters, L.; Pourtois, G.; Schulze, A.; Douhard, B.; Vanherle, W.; Eneman, G.; Richard, O.; Favia, P.; Mitard, J.; Mocuta, D.; Langer, R.; Collaert, N.
	Title	Epitaxial CVD growth of ultra-thin Si passivation layers on strained Ge fin structures			Type	P1 Proceeding
	Year	2017	Publication	Semiconductor Process Integration 10	Abbreviated Journal
	Volume		Issue		Pages	241-252
	Keywords	P1 Proceeding; Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
	Abstract	Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET devices. We use Si4H10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 degrees C. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during the Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions.
	Address
	Corporate Author				Thesis
	Publisher	Electrochemical soc inc	Place of Publication	Pennington	Editor
	Language		Wos	000426269800024	Publication Date	2017-10-17
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume	80	Series Issue	4	Edition
	ISSN	978-1-60768-821-1; 978-1-62332-473-5	ISBN		Additional Links	UA library record; WoS full record
	Impact Factor		Times cited		Open Access	Not_Open_Access
	Notes				Approved	Most recent IF: NA
	Call Number	UA @ lucian @ c:irua:149965			Serial	4966
Permanent link to this record



	Author	Verreck, D.; Verhulst, A.S.; Van de Put, M.L.; Sorée, B.; Magnus, W.; Collaert, N.; Mocuta, A.; Groeseneken, G.
	Title	Self-consistent 30-band simulation approach for (non-)uniformly strained confined heterostructure tunnel field-effect transistors			Type	P1 Proceeding
	Year	2017	Publication	Simulation of Semiconductor Processes and, Devices (SISPAD)AND DEVICES (SISPAD 2017)	Abbreviated Journal
	Volume		Issue		Pages	29-32
	Keywords	P1 Proceeding; Condensed Matter Theory (CMT)
	Abstract	Heterostructures of III-V materials under a mechanical strain are being actively researched to enhance the performance of the tunnel field-effect transistor (TFET). In scaled III-V device structures, however, the interplay between the effects of strain and quantum confinement on the semiconductor band structure and hence the performance is highly non-trivial. We have therefore developed a computationally efficient quantum mechanical simulator Pharos, which enables self-consistent full-zone k.p-based simulations of III-V TFETs under a general non-uniform strain. We present the self-consistent procedure and demonstrate it on confined staggered bandgap GaAs0.5Sb0.5/In0.53Ga0.47As TFETs. We find a large performance degradation due to size-induced quantum confinement compared to non-confined devices. We show that some performance can be regained either by applying a uniform biaxial tensile strain or through the non-uniform strain profile at a lattice-mismatched heterostructure.
	Address
	Corporate Author				Thesis
	Publisher	Ieee	Place of Publication	New york	Editor
	Language		Wos		Publication Date
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	978-4-86348-610-2	ISBN		Additional Links	UA library record; WoS full record
	Impact Factor		Times cited		Open Access
	Notes				Approved	Most recent IF: NA
	Call Number	UA @ lucian @ c:irua:149949			Serial	4978
Permanent link to this record



	Author	Mohammed, M.; Verhulst, A.S.; Verreck, D.; Van de Put, M.; Simoen, E.; Sorée, B.; Kaczer, B.; Degraeve, R.; Mocuta, A.; Collaert, N.; Thean, A.; Groeseneken, G.
	Title	Electric-field induced quantum broadening of the characteristic energy level of traps in semiconductors and oxides			Type	A1 Journal article
	Year	2016	Publication	Journal of applied physics	Abbreviated Journal	J Appl Phys
	Volume	120	Issue	120	Pages	245704
	Keywords	A1 Journal article; Condensed Matter Theory (CMT)
	Abstract	The trap-assisted tunneling (TAT) current in tunnel field-effect transistors (TFETs) is one of the crucial factors degrading the sub-60 mV/dec sub-threshold swing. To correctly predict the TAT currents, an accurate description of the trap is required. Since electric fields in TFETs typically reach beyond 10(6) V/cm, there is a need to quantify the impact of such high field on the traps. We use a quantum mechanical implementation based on the modified transfer matrix method to obtain the trap energy level. We present the qualitative impact of electric field on different trap configurations, locations, and host materials, including both semiconductors and oxides. We determine that there is an electric-field related trap level shift and level broadening. We find that these electric-field induced quantum effects can enhance the trap emission rates. Published by AIP Publishing.
	Address
	Corporate Author				Thesis
	Publisher	American Institute of Physics	Place of Publication	New York, N.Y.	Editor
	Language		Wos	000392174000028	Publication Date	2016-12-26
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0021-8979; 1089-7550	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	2.068	Times cited	6	Open Access
	Notes	; This work was supported by imec's Industrial Affiliation Program. D. Verreck acknowledges the support of a PhD stipend from IWT-Vlaanderen. ;			Approved	Most recent IF: 2.068
	Call Number	UA @ lucian @ c:irua:141481			Serial	4593
Permanent link to this record



	Author	Verreck, D.; Verhulst, A.S.; Van de Put, M.L.; Sorée, B.; Collaert, N.; Mocuta, A.; Thean, A.; Groeseneken, G.
	Title	Uniform strain in heterostructure tunnel field-effect transistors			Type	A1 Journal article
	Year	2016	Publication	IEEE electron device letters	Abbreviated Journal	Ieee Electr Device L
	Volume	37	Issue	37	Pages	337-340
	Keywords	A1 Journal article; Condensed Matter Theory (CMT)
	Abstract	Strain can strongly impact the performance of III-V tunnel field-effect transistors (TFETs). However, previous studies on homostructure TFETs have found an increase in ON-current to be accompanied with a degradation of subthreshold swing. We perform 30-band quantum mechanical simulations of staggered heterostructure p-n-i-n TFETs submitted to uniaxial and biaxial uniform stress and find the origin of the subthreshold degradation to be a reduction of the density of states in the strained case. We apply an alternative configuration including a lowly doped pocket in the source, which allows to take full benefit of the strain-induced increase in ON-current.
	Address
	Corporate Author				Thesis
	Publisher		Place of Publication		Editor
	Language		Wos	000372372100026	Publication Date	2016-01-27
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0741-3106	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	3.048	Times cited	17	Open Access
	Notes	; This work was supported by the imec Industrial Affiliation Program. The work of D. Verreck was supported by the Agency for Innovation by Science and Technology in Flanders. The review of this letter was arranged by Editor Z. Chen. ;			Approved	Most recent IF: 3.048
	Call Number	UA @ lucian @ c:irua:133207			Serial	4271
Permanent link to this record



	Author	Verreck, D.; Verhulst, A.S.; Sorée, B.; Collaert, N.; Mocuta, A.; Thean, A.; Groeseneken, G.
	Title	Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors			Type	P1 Proceeding
	Year	2016	Publication	Solid-State Device Research (ESSDERC), European Conference T2 – 46th European Solid-State Device Research Conference (ESSDERC) / 42nd, European Solid-State Circuits Conference (ESSCIRC), SEP 12-15, 2016, Lausanne, SWITZERLAND	Abbreviated Journal
	Volume		Issue		Pages	412-415
	Keywords	P1 Proceeding; Condensed Matter Theory (CMT)
	Abstract	Because of its localized impact on the band structure, non-uniform strain at the heterojunction between lattice-mismatched materials has the potential to significantly enlarge the design space for tunnel-field effect transistors (TFET). However, the impact of a complex strain profile on TFET performance is difficult to predict. We have therefore developed a 2D quantum mechanical transport formalism capable of simulating the effects of a general non-uniform strain. We demonstrate the formalism for the GaAsxSb(1-x)/InyGa(1-y) As system and show that a performance improvement over a lattice-matched reference is indeed possible, allowing for relaxed requirements on the source doping. We also point out that the added design parameter of mismatch is not free, but limited by the desired effective bandgap at the tunnel junction.
	Address
	Corporate Author				Thesis
	Publisher	Ieee	Place of Publication	New york	Editor
	Language		Wos		Publication Date
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	978-1-5090-2969-3	ISBN		Additional Links	UA library record; WoS full record
	Impact Factor		Times cited		Open Access
	Notes				Approved	Most recent IF: NA
	Call Number	UA @ lucian @ c:irua:138233			Serial	4358
Permanent link to this record



	Author	Verreck, D.; Verhulst, A.S.; Van de Put, M.; Sorée, B.; Magnus, W.; Mocuta, A.; Collaert, N.; Thean, A.; Groeseneken, G.
	Title	Full-zone spectral envelope function formalism for the optimization of line and point tunnel field-effect transistors			Type	A1 Journal article
	Year	2015	Publication	Journal of applied physics	Abbreviated Journal	J Appl Phys
	Volume	118	Issue	118	Pages	134502
	Keywords	A1 Journal article; Condensed Matter Theory (CMT)
	Abstract	Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In0.53Ga0.47As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET. (C) 2015 AIP Publishing LLC.
	Address
	Corporate Author				Thesis
	Publisher	American Institute of Physics	Place of Publication	New York, N.Y.	Editor
	Language		Wos	000362668400025	Publication Date	2015-10-01
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0021-8979; 1089-7550	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	2.068	Times cited	9	Open Access
	Notes	; D. Verreck acknowledges the support of a Ph.D. stipend from the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT-Vlaanderen). This work was supported by imec's Industrial Affiliation Program. ;			Approved	Most recent IF: 2.068; 2015 IF: 2.183
	Call Number	UA @ lucian @ c:irua:128765			Serial	4183
Permanent link to this record



	Author	Verreck, D.; Verhulst, A.S.; Sorée, B.; Collaert, N.; Mocuta, A.; Thean, A.; Groeseneken, G.
	Title	Improved source design for p-type tunnel field-effect transistors : towards truly complementary logic			Type	A1 Journal article
	Year	2014	Publication	Applied physics letters	Abbreviated Journal	Appl Phys Lett
	Volume	105	Issue	24	Pages	243506
	Keywords	A1 Journal article; Condensed Matter Theory (CMT)
	Abstract	Complementary logic based on tunnel field-effect transistors (TFETs) would drastically reduce power consumption thanks to the TFET's potential to obtain a sub-60 mV/dec subthreshold swing (SS). However, p-type TFETs typically do not meet the performance of n-TFETs for direct bandgap III-V configurations. The p-TFET SS stays well above 60 mV/dec, due to the low density of states in the conduction band. We therefore propose a source configuration in which a highly doped region is maintained only near the tunnel junction. In the remaining part of the source, the hot carriers in the exponential tail of the Fermi-Dirac distribution are blocked by reducing the doping degeneracy, either with a source section with a lower doping concentration or with a heterostructure. We apply this concept to n-p-i-p configurations consisting of In0.53Ga0.47As and an InP-InAs heterostructure. 15-band quantum mechanical simulations predict that the configurations with our source design can obtain sub-60 mV/dec SS, with an on-current comparable to the conventional source design. (C) 2014 AIP Publishing LLC.
	Address
	Corporate Author				Thesis
	Publisher	American Institute of Physics	Place of Publication	New York, N.Y.	Editor
	Language		Wos	000346643600076	Publication Date	2014-12-17
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0003-6951;1077-3118;	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	3.411	Times cited	10	Open Access
	Notes	; D. Verreck acknowledges the support of a Ph.D. stipend from the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT-Vlaanderen). This work was supported by imec's Industrial Affiliation Program. ;			Approved	Most recent IF: 3.411; 2014 IF: 3.302
	Call Number	UA @ lucian @ c:irua:122798			Serial	1568
Permanent link to this record



	Author	Verhulst, A.S.; Verreck, D.; Pourghaderi, M.A.; Van de Put, M.; Sorée, B.; Groeseneken, G.; Collaert, N.; Thean, A.V.-Y.
	Title	Can p-channel tunnel field-effect transistors perform as good as n-channel?			Type	A1 Journal article
	Year	2014	Publication	Applied physics letters	Abbreviated Journal	Appl Phys Lett
	Volume	105	Issue	4	Pages	043103
	Keywords	A1 Journal article; Condensed Matter Theory (CMT)
	Abstract	We show that bulk semiconductor materials do not allow perfectly complementary p- and n-channel tunnel field-effect transistors (TFETs), due to the presence of a heavy-hole band. When tunneling in p-TFETs is oriented towards the gate-dielectric, field-induced quantum confinement results in a highest-energy subband which is heavy-hole like. In direct-bandgap IIIV materials, the most promising TFET materials, phonon-assisted tunneling to this subband degrades the subthreshold swing and leads to at least 10x smaller on-current than the desired ballistic on-current. This is demonstrated with quantum-mechanical predictions for p-TFETs with tunneling orthogonal to the gate, made out of InP, In0.53Ga0.47As, InAs, and a modified version of In0.53Ga0.47As with an artificially increased conduction-band density-of-states. We further show that even if the phonon-assisted current would be negligible, the build-up of a heavy-hole-based inversion layer prevents efficient ballistic tunneling, especially at low supply voltages. For p-TFET, a strongly confined n-i-p or n-p-i-p configuration is therefore recommended, as well as a tensily strained line-tunneling configuration. (C) 2014 AIP Publishing LLC.
	Address
	Corporate Author				Thesis
	Publisher	American Institute of Physics	Place of Publication	New York, N.Y.	Editor
	Language		Wos	000341152600067	Publication Date	2014-07-30
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0003-6951; 1077-3118	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	3.411	Times cited	8	Open Access
	Notes	; This work was supported by imec's industrial application program. D. Verreck acknowledges the support of a Ph.D. stipend from the Institute for Promotion of Innovation through Science and Technology in Flanders (IWT). ;			Approved	Most recent IF: 3.411; 2014 IF: 3.302
	Call Number	UA @ lucian @ c:irua:134433			Serial	4587
Permanent link to this record



	Author	Smets, Q.; Verreck, D.; Verhulst, A.S.; Rooyackers, R.; Merckling, C.; Van De Put, M.; Simoen, E.; Vandervorst, W.; Collaert, N.; Thean, V.Y.; Sorée, B.; Groeseneken, G.; Heyns, M.M.;
	Title	InGaAs tunnel diodes for the calibration of semi-classical and quantum mechanical band-to-band tunneling models			Type	A1 Journal article
	Year	2014	Publication	Journal of applied physics	Abbreviated Journal	J Appl Phys
	Volume	115	Issue	18	Pages	184503-184509
	Keywords	A1 Journal article; Condensed Matter Theory (CMT)
	Abstract	Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kane's formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In0.53Ga0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In0.53Ga0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance compared to MOSFET.
	Address
	Corporate Author				Thesis
	Publisher	American Institute of Physics	Place of Publication	New York, N.Y.	Editor
	Language		Wos	000336919400048	Publication Date	2014-05-14
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0021-8979;1089-7550;	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	2.068	Times cited	34	Open Access
	Notes	; Quentin Smets and Devin Verreck gratefully acknowledge the support of a Ph. D. stipend from IWT-Vlaanderen. This work was supported by imec's industrial affiliation program. The authors thank Kim Baumans, Johan Feyaerts, Johan De Cooman, Alireza Alian, and Jos Moonens for their support in process development; Bastien Douhard and Joris Delmotte for SIMS characterization; Alain Moussa for AFM characterization; Joris Van Laer and Tom Daenen for their support in electrical characterization; Kuo-Hsing Kao, Mehbuba Tanzid, and Ali Pourghaderi for their support in modeling. ;			Approved	Most recent IF: 2.068; 2014 IF: 2.183
	Call Number	UA @ lucian @ c:irua:118009			Serial	1667
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	Author	Verreck, D.; Van de Put, M.; Sorée, B.; Verhulst, A.S.; Magnus, W.; Vandenberghe, W.G.; Collaert, N.; Thean, A.; Groeseneken, G.
	Title	Quantum mechanical solver for confined heterostructure tunnel field-effect transistors			Type	A1 Journal article
	Year	2014	Publication	Journal of applied physics	Abbreviated Journal	J Appl Phys
	Volume	115	Issue	5	Pages	053706-53708
	Keywords	A1 Journal article; Condensed Matter Theory (CMT)
	Abstract	Heterostructure tunnel field-effect transistors (HTFET) are promising candidates for low-power applications in future technology nodes, as they are predicted to offer high on-currents, combined with a sub-60 mV/dec subthreshold swing. However, the effects of important quantum mechanical phenomena like size confinement at the heterojunction are not well understood, due to the theoretical and computational difficulties in modeling realistic heterostructures. We therefore present a ballistic quantum transport formalism, combining a novel envelope function approach for semiconductor heterostructures with the multiband quantum transmitting boundary method, which we extend to 2D potentials. We demonstrate an implementation of a 2-band version of the formalism and apply it to study confinement in realistic heterostructure diodes and p-n-i-n HTFETs. For the diodes, both transmission probabilities and current densities are found to decrease with stronger confinement. For the p-n-i-n HTFETs, the improved gate control is found to counteract the deterioration due to confinement. (C) 2014 AIP Publishing LLC.
	Address
	Corporate Author				Thesis
	Publisher	American Institute of Physics	Place of Publication	New York, N.Y.	Editor
	Language		Wos	000331645900040	Publication Date	2014-02-05
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0021-8979;1089-7550;	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	2.068	Times cited	15	Open Access
	Notes	; D. Verreck acknowledges the support of a Ph.D. stipend from the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT-Vlaanderen). This work was supported by imec's Industrial Affiliation Program. ;			Approved	Most recent IF: 2.068; 2014 IF: 2.183
	Call Number	UA @ lucian @ c:irua:115825			Serial	2780
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	Author	Verhulst, A.S.; Verreck, D.; Smets, Q.; Kao, K.-H.; Van de Put, M.; Rooyackers, R.; Sorée, B.; Vandooren, A.; De Meyer, K.; Groeseneken, G.; Heyns, M.M.; Mocuta, A.; Collaert, N.; Thean, A.V.-Y.
	Title	Perspective of tunnel-FET for future low-power technology nodes			Type	P1 Proceeding
	Year	2014	Publication	2014 Ieee International Electron Devices Meeting (iedm)	Abbreviated Journal
	Volume		Issue		Pages
	Keywords	P1 Proceeding; Condensed Matter Theory (CMT)
	Abstract
	Address
	Corporate Author				Thesis
	Publisher	Ieee	Place of Publication	New york	Editor
	Language		Wos		Publication Date
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	978-1-4799-8000-0	ISBN		Additional Links	UA library record; WoS full record
	Impact Factor		Times cited		Open Access
	Notes				Approved	Most recent IF: NA
	Call Number	UA @ lucian @ c:irua:144789			Serial	4679
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	Author	Pokatilov, E.P.; Fomin, V.M.; Balaban, S.N.; Gladilin, V.N.; Klimin, S.N.; Devreese, J.T.; Magnus, W.; Schoenmaker, W.; Collaert, N.; van Rossum, M.; de Meyer, K.
	Title	Distribution of fields and charge carriers in cylindrical nanosize silicon-based metal-oxide-semiconductor structures			Type	A1 Journal article
	Year	1999	Publication	Journal Of Applied Physics	Abbreviated Journal	J Appl Phys
	Volume	85	Issue		Pages	6625-6631
	Keywords	A1 Journal article; Electron Microscopy for Materials Science (EMAT);
	Abstract
	Address
	Corporate Author				Thesis
	Publisher	American Institute of Physics	Place of Publication	New York, N.Y.	Editor
	Language		Wos	000079871200053	Publication Date	2002-07-26
	Series Editor		Series Title		Abbreviated Series Title
	Series Volume		Series Issue		Edition
	ISSN	0021-8979;	ISBN		Additional Links	UA library record; WoS full record; WoS citing articles
	Impact Factor	2.068	Times cited	16	Open Access
	Notes				Approved	Most recent IF: 2.068; 1999 IF: 2.275
	Call Number	UA @ lucian @ c:irua:24444			Serial	743
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