Abstract: Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET devices. We use Si4H10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 degrees C. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during the Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions.

Abstract: We discuss the selection and assessment of alternative metals by a combination of ab initio computation of electronic properties, experimental resistivity assessments, and calibrated line resistance models. Pt-group metals as well as Nb are identified as the most promising elements, with Ru showing the best combination of material properties and process maturity. An experimental assessment of the resistivity of Ru, Ir, and Co lines down to similar to 30 nm(2) is then used to devise compact models for line and via resistance that can be compared to Cu predictions. The main advantage of alternative metals originates from the possibility for barrierless metallization.

Abstract: The fine balance between dipole-field energy and anion drift force defines the switching mechanism during polarization reversal: for the first time we show that only Pbcm mechanism obeys the ferroelectric switching physics, whereas P4(2)/nmc (or any other) mechanism does not. However, with lower energy barrier, it represents an important antiferroelectric mechanism. Constraints relaxation can lead to 90 degrees polarization rotation (domain deactivation). Intrinsically, the Si/VO-doping can switch faster than undoped HfO2 or HfZrOx. Theoretical Arrhenius model / intrinsic material switching (DFT) overestimates the switching speed extracted from experiments.

Abstract: The scalability potential of low resistivity ternary metallic alloys (MAX) as an interconnect medium has been benchmarked against copper through first-principle simulations. We report that some carbon and nitrogen MAX phases have the potential to display a reduced sensitivity of their intrinsic resistivity to scaling, while showing improved electromigration properties.

Abstract: uIn this work, we discuss three novel Ti (germano-)silicidation techniques featuring respectively the pre-contact amorphization implantation (PCAI), the TiSi co-deposition, and Ti atomic layer deposition (ALD). All three techniques form TiSix(Ge-y) contacts with ultralow contact resistivity (rho(c)) of (1-3)x10(-9) Omega.cm(2) on both highly doped n-Si and p-SiGe substrates: these techniques meet rho(c) requirement of 5-14 nm CMOS technology and feature unified CMOS contact solutions. We further discuss the compatibility of these techniques to the realistic CMOS transistor fabrication.

Abstract: The properties of alternative metals to Cu and W for interconnect applications are reviewed based on first-principles simulations and benchmarked in terms of intrinsic bulk resistivity and electromigration.

Abstract: The structural and electronic properties of silicene and germanene on metallic and non-metallic substrates are investigated theoretically, using first-principles simulations. We first study the interaction of silicene with Ag(111) surfaces, focusing on the (4x4) silicene/Ag structure. Due to symmetry breaking in the silicene layer (nonequivalent number of top and bottom Si atoms), silicene is predicted to be semiconducting, with a computed energy gap of about 0.3 eV. However, the charge transfer occurring at the silicene/Ag(111) interface leads to an overall metallic system. We next investigate the interaction of silicene and germanene with hexagonal non-metallic substrates, namely ZnS and ZnSe. On reconstructed (semiconducting) (0001) ZnS or ZnSe surfaces, silicene and germanene are found to be semiconducting. Remarkably, the nature (indirect or direct) and magnitude of their energy band gap can be controlled by an out-of-plane electric field.

Abstract: Crystalline superlattices consisting of alternating periods of Si layers and O-atomic layers are potential new channel materials for scaled CMOS devices. In this letter, we investigate Chemical Vapor Deposition (CVD) for the controlled deposition of O-atoms with O-3 as precursor on Si(100) substrates and Si epitaxy on the O-layer. The O-3 reaction at 50 degrees C on the H-terminated Si results in the formation of Si-OH and/or Si-O-Si-H surface species with monolayer O-content. Defect-free epitaxial growth of Si on an O-layer containing 6.4E+14 O-atoms/cm(2) is achieved from SiH4 at 500 degrees C. (C) 2013 The Electrochemical Society. All rights reserved.

Abstract: We derive an analytical model for the electrostatics and the drive current in a silicon nanowire operating in JFET mode. We show that there exists a range of nanowire radii and doping densities for which the nanowire JFET satisfies reasonable device characteristics. For thin nanowires we have developed a self-consistent quantum mechanical model to obtain the electronic structure.

Abstract: Strained SiGe heterostructure-on-insulator (0 0 1) and (1 1 0) PMOSFETs are investigated including important aspects like CV characteristics, mobility, and ON current. The simulations are based on the self-consistent solution of 6 × 6 k · p Schrödinger Equation, multi subband Boltzmann Transport Equation and Poisson Equation, and capture size quantization, strain, crystallographic orientation, and SiGe alloy effects on a solid physical basis. The simulation results are validated by comparison with different experimental data sources. The simulation results show that the strained SiGe HOI PMOSFET with (1 1 0) surface orientation has a higher gate capacitance and a much higher mobility and ON current compared to a similar device with the traditional (0 0 1) surface orientation.

Abstract: <script type='text/javascript'>document.write(unpmarked('The crystal and defect structure of SnS crystals grown using chemical vapour deposition for application in electronic devices are investigated. The structural analysis shows the presence of two distinct crystal morphologies, that is thin flakes with lateral sizes up to 50 m and nanometer scale thickness, and much thicker but smaller crystallites. Both show similar Raman response associated with SnS. The structural analysis with transmission electron microscopy shows that the flakes are single crystals of -SnS with [010] normal to the substrate. Parallel with the surface of the flakes, lamellae with varying thickness of a new SnS phase are observed. High-resolution transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), first-principles simulations (DFT) and nanobeam diffraction (NBD) techniques are employed to characterise this phase in detail. DFT results suggest that the phase is a strain stabilised \u0027 one grown epitaxially on the -SnS crystals. TEM analysis shows that the crystallites are also -SnS with generally the [010] direction orthogonal to the substrate. Contrary to the flakes the crystallites consist of two to four grains which are tilted up to 15 degrees relative to the substrate. The various grain boundary structures and twin relations are discussed. Under high-dose electron irradiation, the SnS structure is reduced and -Sn formed. It is shown that this damage only occurs for SnS in direct contact with SiO2. Lay description SnS is a p-type semiconductor, which has attracted significant interest for electronic devices due to its unique properties, low-toxicity and abundance of Sn in nature. Although in the past it has been most extensively studied as the absorber material in solar cells, it has recently garnered interest for application as a p-type two-dimensional semiconductor in nanoelectronic devices due to its anisotropic layered structure similar to the better known phosphorene. Tin sulphide can take the form of several phases and the electronic properties of the material depend strongly on its crystal structure. It is therefore crucial to study the crystal structure of the material in order to predict the electronic properties and gain insight into the growth mechanism. In this work, SnS crystals deposited using a chemical vapour deposition technique are investigated extensively for their crystal and defect structure using transmission electron microscopy (TEM) and related techniques. We find the presence of two distinct crystal morphologies, that is thin flakes with lateral sizes up to 50 m and nm scale thickness, and much thicker but smaller crystallites. The flakes are single crystals of -SnS and contain lamellae with varying thickness of a different phase which appear to be -SnS at first glance. High-resolution scanning transmission electron microscopy is used to characterise these lamellae where the annular bright field (ABF) mode better reveals the position of the sulphur columns. The sulphur columns in the lamellae are found to be shifted relative to the -SnS structure which indicates the formation of a new phase which is a distorted version of the phase which we tentatively refer to as \u0027-SnS. Simulations based on density functional theory (DFT) are used to model the interface and a similar shift of sulphur columns in the -SnS layer is observed which takes place as a result of strong interaction at the interface between the two phases resulting in strain transfer. Nanobeam electron diffraction (NBD) is used to map the lattice mismatch in the thickness of the flakes which reveals good in-plane matching and some expansion out-of-plane in the lamellae. Contrary to the flakes the crystallites are made solely of -SnS and consist of two to four grains which are tilted up to 15 degrees relative to the substrate. The various grain boundary structures and twin relations are discussed. At high electron doses, SnS is reduced to -Sn, however the damage occurs only for SnS in direct contact with SiO2.'));

Abstract: The bulk properties of elementary metals and copper based binary alloys have been investigated using automated first-principles simulations to evaluate their potential to replace copper and tungsten as interconnecting wires in the coming CMOS technology nodes. The intrinsic properties of the screened candidates based on their cohesive energy and on their electronic properties have been used as a metrics to reflect their resistivity and their sensitivity to electromigration. Using these values, the 'performances' of the alloys have been benchmarked with respect to the Cu and W ones. It turns out that for some systems, alloying Cu with another element leads to a reduced tendency to electromigration. This is however done at the expense of a decrease of the conductivity of the alloy with respect to the bulk metal. (C) 2014 The Electrochemical Society. All rights reserved.

Abstract: In this contribution, we report a fundamental study of the factors that set the contact resistivity between metals and highly doped n-type 2D and 3D semiconductors. We investigate the case of n-type doped Si contacted with amorphous TiSi combining first principles calculations with Non-Equilibrium Green functions transport simulations. The evolution of the intrinsic contact resistivity with the doping concentration is found to saturate at similar to 2 x 10(-10) Omega.cm(2) for the case of TiSi and imposes an intrinsic limit to the ultimate contact resistance achievable for n-doped Silamorphous-TiSi (aTiSi). The limit arises from the intrinsic properties of the semiconductors and of the metals such as their electron effective masses and Fermi energies. We illustrate that, in this regime, contacting heavy electron effective mass metals with semiconductor helps reducing the interface intrinsic contact resistivity. This observation seems to hold true regardless of the 3D character of the semiconductor, as illustrated for the case of three 2D semiconducting materials, namely MoS2, ZrS2 and HfS2. (C) The Author(s) 2018. Published by ECS.

Abstract: Si:C and Si:C:P alloys are potential candidates for source-drain stressor applications in n-type Fin Field Effect Transistors (FinFETs). Increasing the C content to achieve high strain results in the arrangement of C atoms as third nearest neighbors (3nn) in the Si: C lattice. During thermal annealing, the presence of C atoms as 3nn may promote clustering at the interstitial sites, causing loss of stress. The concentration of C atoms as 3nn is reduced by the incorporation of a small amount of Ge atoms during the growth, whereas in-situ P doping does not influence this 3nn distribution [J Solid State Sci. Technol vol 6, p 755, 2017]. Small amounts of Ge are provided during low temperature selective epitaxial growth scheme, which are based on cyclic deposition and etching (CDE). In this work, we aim to provide physical insights into the aforementioned phenomena, to understand the behavior of 3nn C atoms and the types of defects that are formed in the annealed Si: C films. Using ab-initio simulations, the Ge-C interaction in the Si matrix is investigated and this insight is used to explain how the Ge incorporation leads to a reduced 3nn distribution of the C atoms. The interaction between C and P in the Si: C: P films is also investigated to explain why the P incorporation has not led to a reduction in the 3nn distribution. We then report on the Raman characterization of Si: C layers subjected to post epi annealing. As the penetration depth of the laser is dependent on the wavelength, Raman measurements at two different wavelengths enable us to probe the depth distribution of 3nn C atoms after applying different annealing conditions. We observed a homogeneous loss in 3nn C throughout the layer. Whereas in the kinematic modeling of high resolution X-ray diffraction spectra, a gradient in the substitutional C loss was observed close to the epitaxial layer/substrate interface. This gradient can be due to the out diffusion of C atoms into the Si substrate or to the formation of interstitial C clusters, which cannot be distinguished in HR-XRD. Deep Level Transient Spectroscopy indicated that the prominent out-diffusing species was interstitial CO complex while the interstitial C defects were also prevalent in the epi layer. (c) 2019 The Electrochemical Society.

Abstract: First-principles simulations were employed to gain atomistic insights on the working principles of amorphous HfO2 based Resistive Random Access Memory stack: the nature of the defect responsible for the switching between the High and Low Resistive States has been unambiguously identified to be the substoichiometric Hf sites (commonly called oxygen vacancy-V-O) and the kinetics of the process have been investigated through the study of O diffusion. Also the role of each material layer in the TiN/HfO2/Hf/TiN RRAM stack and the impact of the deposition techniques have been examined: metallic Hf sputtering is needed to provide an oxygen exchange layer that plays the role of defect buffer. TiN shall be a good defect barrier for O but a bad defect buffer layer. A possible scenario to explain the device degradation (switching failure) mechanism has been proposed – the relaxation of the metastable amorphous phase towards crystalline structure leads to denser, more structured cluster that can increase the defect migration barriers. (C) 2013 Elsevier B.V. All rights reserved.