Abstract: The observation of a significant temperature-dependent variation in the ${I}$ – ${V}$ characteristics of tunneling devices is often interpreted as a signature of a trap-assisted-tunneling dominated current. In this letter, we use a ballistic 2D quantum-mechanical simulator, calibrated using the measured temperature-dependent ${I}$ – ${V}$ characteristics of Esaki diodes, to demonstrate that the temperature dependence of band-to-band tunneling (BTBT) current can vary significantly in both Esaki diodes and tunnel FETs. The variation of BTBT current with temperature is impacted by doping concentration, gate voltage, possible presence of a highly-doped pocket at the tunnel junction, and material.

Abstract: Strain can strongly impact the performance of III-V tunnel field-effect transistors (TFETs). However, previous studies on homostructure TFETs have found an increase in ON-current to be accompanied with a degradation of subthreshold swing. We perform 30-band quantum mechanical simulations of staggered heterostructure p-n-i-n TFETs submitted to uniaxial and biaxial uniform stress and find the origin of the subthreshold degradation to be a reduction of the density of states in the strained case. We apply an alternative configuration including a lowly doped pocket in the source, which allows to take full benefit of the strain-induced increase in ON-current.

Abstract: Quantum phase slips represent a coherent mechanism to couple flux states of a superconducting loop. Since their first direct observation, there have been substantial developments in building charge-insensitive quantum phase-slip circuits. At the heart of these devices is a weak link, often a nanowire, interrupting a superconducting loop. Owing to the very small cross-sectional area of such a nanowire, quantum phase slip rates in the gigahertz range can be achieved. Instead, here we present the use of a bias voltage across a superconducting loop to electrostatically induce a weak link, thereby amplifying the rate of quantum phase slips without physically interrupting the loop. Our simulations reveal that the bias voltage modulates the free energy barrier between subsequent flux states in a very controllable fashion, providing a route towards a phase-slip flux qubit with a broadly tunable transition frequency.

Abstract: Three-dimensional topological insulator (3D TI) nanowires display remarkable magnetotransport properties that can be attributed to their spin-momentum-locked surface states such as quasiballistic transport and Aharonov-Bohm oscillations. Here, we focus on the transport properties of a 3D TI nanowire with a gated section that forms an electronic Fabry-Perot (FP) interferometer that can be tuned to act as a surface-state filter or energy barrier. By tuning the carrier density and length of the gated section of the wire, the interference pattern can be controlled and the nanowire can become fully transparent for certain topological surface-state input modes while completely filtering out others. We also consider the interplay of FP interference with an external magnetic field, with which Klein tunneling can be induced, and transverse asymmetry of the gated section, e.g. due to a top-gated structure, which displays an interesting analogy with Rashba nanowires. Due to its rich conductance phenomenology, we propose a 3D TI nanowire with gated section as an ideal setup for a detailed transport-based characterization of 3D TI nanowire surface states near the Dirac point, which could be useful towards realizing 3D TI nanowire-based topological superconductivity and Majorana bound states.

Abstract: Today, further downscaling of mobile electronic devices poses serious problems, such as energy consumption and local heat dissipation. In this context, spin wave majority gates made of very thin ferromagnetic films may offer a viable alternative. However, similar downscaling of magnetic thin films eventually enforces the latter to operate as quasi-2D magnets, the magnetic properties of which are not yet fully understood, especially those related to anisotropies and external magnetic fields in arbitrary directions. To this end, we have investigated the behaviour of an easy-plane and easy-axis anisotropic ferromagnet-both in two and three dimensions-subjected to a uniform magnetic field, applied along an arbitrary direction. In this paper, a spin-1/2 Heisenberg Hamiltonian with anisotropic exchange interactions is solved using double-time temperature-dependent Green's functions and the Tyablikov decoupling approximation. We determine various magnetic properties such as the Curie temperature and the magnetization as a function of temperature and the applied magnetic field, discussing the impact of the system's dimensionality and the type of anisotropy. The magnetic reorientation transition taking place in anisotropic Heisenberg ferromagnets is studied in detail. Importantly, spontaneous magnetization is found to be absent for easy-plane 2D spin systems with short range interactions.

Abstract: Fermi's golden rule underpins the investigation of mobile carriers propagating through various solids, being a standard tool to calculate their scattering rates. As such, it provides a perturbative estimate under the implicit assumption that the effect of the interaction Hamiltonian which causes the scattering events is sufficiently small. To check the validity of this assumption, we present a general framework to derive simple validity criteria in order to assess whether the scattering rates can be trusted for the system under consideration, given its statistical properties such as average size, electron density, impurity density et cetera. We derive concrete validity criteria for metallic nanowires with conduction electrons populating a single parabolic band subjected to different elastic scattering mechanisms: impurities, grain boundaries and surface roughness.

Abstract: Switching induced by spin-orbit torque (SOT) is being vigorously explored, as it allows the control of magnetization using an in-plane current, which enables a three-terminal magnetic-tunnel-junction geometry with isolated read and write paths. This significantly improves the device endurance and the read stability, and allows reliable subnanosecond switching. Tungsten in the beta phase, beta-W, has the largest reported antidamping SOT charge-to-spin conversion ratio (theta(AD) approximate to -60%) for heavy metals. However, beta-W has a limitation when one is aiming for reliable technology integration: the beta phase is limited to a thickness of a few nanometers and enters the alpha phase above 4 nm in our samples when industry-relevant deposition tools are used. Here, we report our approach to extending the range of beta-W, while simultaneously improving the SOT efficiency by introducing N and O doping of W. Resistivity and XRD measurements confirm the extension of the beta phase from 4 nm to more than 10 nm, and transport characterization shows an effective SOT efficiency larger than -44.4% (reaching approximately -60% for the bulk contribution). In addition, we demonstrate the possibility of controlling and enhancing the perpendicular magnetic anisotropy of a storage layer (Co-Fe-B). Further, we integrate the optimized W(O, N) into SOT magnetic random-access memory (SOT-MRAM) devices and project that, for the same thickness of SOT material, the switching current decreases by 25% in optimized W(O, N) compared with our standard W. Our results open the path to using and further optimizing W for integration of SOT-MRAM technology.

Abstract: Utilizing magnetic tunnel junctions (MTJs) for write/read and fast spin-orbit-torque (SOT)-driven domain-wall (DW) motion for propagation, enables non-volatile logic and majority operations, representing a breakthrough in the implementation of nanoscale DW logic devices. Recently, current-driven DW logic gates have been demonstrated via magnetic imaging, where the Dzyaloshinskii-Moriya interaction (DMI) induces chiral coupling between perpendicular magnetic anisotropy (PMA) regions via an in-plane (IP) oriented region. However, full electrical operation of nanoscale DW logic requires electrical write/read operations and a method to pattern PMA and IP regions compatible with the fabrication of PMA MTJs. Here, we study the use of a Hybrid Free Layer (HFL) concept to combine an MTJ stack with DW motion materials, and He+ ion irradiation to convert the stack from PMA to IP. First, we investigate the free layer thickness dependence of 100-nm diameter HFL-MTJ devices and find an optimal CoFeB thickness, from 7 to 10 angstrom, providing high tunneling magnetoresistance (TMR) readout and efficient spin-transfer torque (STT) writing. We then show that high DMI materials, like Pt/Co, can be integrated into an MTJ stack via interlayer exchange coupling with the CoFeB free layer. In this design, DMI values suitable for SOT-driven DW motion are measured by asymmetric bubble expansion. Finally, we demonstrate that He+ irradiation reliably converts the coupled free layers from PMA to IP. These findings offer a path toward the integration of fully electrically controlled DW logic circuits.

Abstract: In this work we investigate quantum ballistic transport in ultrasmall junctionless and inversion mode semiconducting nanowire transistors within the framework of the self-consistent Schrödinger-Poisson problem. The quantum transmitting boundary method is used to generate open boundary conditions between the active region and the electron reservoirs. We adopt a subband decomposition approach to make the problem numerically tractable and make a comparison of four different numerical approaches to solve the self-consistent Schrödinger-Poisson problem. Finally we discuss the IV-characteristics for small (r≤5 nm) GaAs nanowire transistors. The novel junctionless pinch-off FET or junctionless nanowire transistor is extensively compared with the gate-all-around (GAA) nanowire MOSFET.

Abstract: The dynamics of electrons and holes propagating through the nano-scaled channels of modern semiconductor devices can be seen as a widespread manifestation of non-equilibrium statistical physics and its ruling principles. In this respect both the devices that are pushing conventional CMOS technology towards the final frontiers of Moores law and the upcoming set of alternative, novel nanostructures grounded on entirely new concepts and working principles, provide an almost unlimited playground for assessing physical models and numerical techniques emerging from classical and quantum mechanical non-equilibrium theory. In this paper we revisit the Boltzmann as well as the WignerBoltzmann equation which offers a valuable platform to study transport of charge carriers taking part in drive currents. We focus on a numerical procedure that regained attention recently as an alternative tool to solve the time-dependent Boltzmann equation for inhomogeneous systems, such as the channel regions of field-effect transistors, and we discuss its extension to the WignerBoltzmann equation. Furthermore, we pay attention to the calculation of tunneling leakage currents. The latter typically occurs in nano-scaled transistors when part of the carrier distribution sustaining the drive current is found to tunnel into the gate due the presence of an ultra-thin insulating barrier separating the gate from the channel region. In particular, we discuss the paradox related to the very existence of leakage currents established by electrons occupying quasi-bound states, while the (real) wave functions of the latter cannot carry net currents. Finally, we describe a simple model to resolve the paradox as well as to estimate gate currents provided the local carrier generation rates largely exceed the tunneling rates.

Abstract: We derive an analytical model for the electrostatics and the drive current in a silicon nanowire operating in JFET mode. We show that there exists a range of nanowire radii and doping densities for which the nanowire JFET satisfies reasonable device characteristics. For thin nanowires we have developed a self-consistent quantum mechanical model to obtain the electronic structure.

Abstract: A spin wave majority fork-like structure with feature size of 40 nm, is presented and investigated, through micromagnetic simulations. The structure consists of three merging out-of-plane magnetization spin wave buses and four magneto-electric cells serving as three inputs and an output. The information of the logic signals is encoded in the phase of the transmitted spin waves and subsequently stored as direction of magnetization of the magneto-electric cells upon detection. The minimum dimensions of the structure that produce an operational majority gate are identified. For all input combinations, the detection scheme employed manages to capture the majority phase result of the spin wave interference and ignore all reflection effects induced by the geometry of the structure. (C) 2017 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

Abstract: <script type='text/javascript'>document.write(unpmarked('Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality – the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 mu m(2) for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.'));

Abstract: Major obstacles in current CMOS technology, such as the interconnect bottleneck and thermal heat management, can be overcome by employing subwavelength-scaled light in plasmonic waveguides and devices. In this work, a plasmonic structure that implements the majority (MAJ) gate function is designed and thoroughly studied through simulations. The structure consists of three merging waveguides, serving as the MAJ gate inputs. The information of the logic signals is encoded in the phase of transmitted surface plasmon polaritons (SPP). SPPs are excited at all three inputs and the phase of the output SPP is determined by theMAJof the input phases. The operating dimensions are identified and the functionality is verified for all input combinations. This is the first reported simulation of a plasmonic MAJ gate and thus contributes to the field of optical computing at the nanoscale. (C) 2017 Author(s).

Abstract: Discrepancies exist between the theoretically predicted and experimentally measured performance of band-to-band tunneling devices, such as Esaki diodes and tunnel field-effect transistors (TFETs). We resolve this discrepancy for highly-doped, direct-bandgap Esaki diodes by successfully calibrating a semi-classical model for high-doping-induced ballistic band-tails tunneling currents at multiple temperatures with two In0.53Ga0.47As Esaki diodes using their SIMS doping profiles, C-V characteristics and their forward-bias current density in the negative differential resistance (NDR) regime. The current swing in the NDR regime is shown not to be linked to the band-tails Urbach energy. We further demonstrate theoretically that the calibrated band-tails contribution is also the dominant band-tails contribution to the subthreshold swing of the corresponding TFETs. Lastly, we verify that the presented procedure is applicable to all direct-bandgap semiconductors by successfully applying it to InAs Esaki diodes in literature.