Abstract: The capacitance-voltage (C-V) characteristic is calculated for p-type In_0.53Ga_0.47As metal-oxide-semiconductor (MOS) structures based on a self-consistent PoissonSchrödinger solution. For strong inversion, charge quantization leads to occupation of the satellite valleys which appears as a sharp increase in the capacitance toward the oxide capacitance. The results indicate that the charge quantization, even in the absence of interface defects (D_it), is a contributing factor to the experimental observation of an almost symmetric C-V response for In_0.53Ga_0.47As MOS structures. In addition, nonparabolic corrections are shown to enhance the depopulation of the Γ valley, shifting the capacitance increase to lower inversion charge densities.

Abstract: Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.

Abstract: Because of its localized impact on the band structure, non-uniform strain at the heterojunction between lattice-mismatched materials has the potential to significantly enlarge the design space for tunnel-field effect transistors (TFET). However, the impact of a complex strain profile on TFET performance is difficult to predict. We have therefore developed a 2D quantum mechanical transport formalism capable of simulating the effects of a general non-uniform strain. We demonstrate the formalism for the GaAsxSb(1-x)/InyGa(1-y) As system and show that a performance improvement over a lattice-matched reference is indeed possible, allowing for relaxed requirements on the source doping. We also point out that the added design parameter of mismatch is not free, but limited by the desired effective bandgap at the tunnel junction.

Abstract: We explain the basic operation of a nanowire pinch-off FET and graphene nanoribbon tunnelFET. For the nanowire pinch-off FET we construct an analytical model to obtain the threshold voltage as a function of radius and doping density. We use the gradual channel approximation to calculate the current-voltage characteristics of this device and we show that the nanowire pinch-off FET has a subthreshold slope of 60 mV/dec and good ION and ION/IOFF ratios. For the graphene nanoribbon tunnelFET we show that an improved analytical model yields more realistic results for the transmission probability and hence the tunneling current. The first simulation results for the graphene nanoribbon tunnelFET show promising subthreshold slopes.

Abstract: Switching induced by spin-orbit torque (SOT) is being vigorously explored, as it allows the control of magnetization using an in-plane current, which enables a three-terminal magnetic-tunnel-junction geometry with isolated read and write paths. This significantly improves the device endurance and the read stability, and allows reliable subnanosecond switching. Tungsten in the beta phase, beta-W, has the largest reported antidamping SOT charge-to-spin conversion ratio (theta(AD) approximate to -60%) for heavy metals. However, beta-W has a limitation when one is aiming for reliable technology integration: the beta phase is limited to a thickness of a few nanometers and enters the alpha phase above 4 nm in our samples when industry-relevant deposition tools are used. Here, we report our approach to extending the range of beta-W, while simultaneously improving the SOT efficiency by introducing N and O doping of W. Resistivity and XRD measurements confirm the extension of the beta phase from 4 nm to more than 10 nm, and transport characterization shows an effective SOT efficiency larger than -44.4% (reaching approximately -60% for the bulk contribution). In addition, we demonstrate the possibility of controlling and enhancing the perpendicular magnetic anisotropy of a storage layer (Co-Fe-B). Further, we integrate the optimized W(O, N) into SOT magnetic random-access memory (SOT-MRAM) devices and project that, for the same thickness of SOT material, the switching current decreases by 25% in optimized W(O, N) compared with our standard W. Our results open the path to using and further optimizing W for integration of SOT-MRAM technology.

Abstract: In tunnel field-effect transistors, trap-assisted tunneling (TAT) is one of the probable causes for degraded subthreshold swing. The accurate quantum-mechanical (QM) assessment of TAT currents also requires a QM treatment of phonon-assisted tunneling (PAT) currents. Therefore, we present a multi-band PAT current formalism within the framework of the quantum transmitting boundary method. An envelope function approximation is used to construct the electron-phonon coupling terms corresponding to local Frohlich-based phonon-assisted inter-band tunneling in direct-bandgap III-V semiconductors. The PAT current density is studied in up to 100 nm long and 20 nm wide p-n diodes with the 2- and 15-band material description of our formalism. We observe an inefficient electron-phonon coupling across the tunneling junction. We further demonstrate the dependence of PAT currents on the device length, for our non-self-consistent formalism which neglects changes in the electron distribution function caused by the electron-phonon coupling. Finally, we discuss the differences in doping dependence between direct band-to-band tunneling and PAT current. Published under license by AIP Publishing.

Abstract: The Zener tunneling current flowing through a biased, abrupt p-n junction embedded in a cylindrical silicon nanowire is calculated. As the band gap becomes indirect for sufficiently thick wires, Zener tunneling and its related transitions between the valence and conduction bands are mediated by short-wavelength phonons interacting with mobile electrons. Therefore, not only the high electric field governing the electrons in the space-charge region but also the transverse acoustic (TA) and transverse optical (TO) phonons have to be incorporated in the expression for the tunneling current. The latter is also affected by carrier confinement in the radial direction and therefore we have solved the Schrodinger and Poisson equations self-consistently within the effective mass approximation for both conduction and valence band electrons. We predict that the tunneling current exhibits a pronounced dependence on the wire radius, particularly in the high-bias regime. (C) 2012 Elsevier Ltd. All rights reserved.

Abstract: <script type='text/javascript'>document.write(unpmarked('Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality – the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 mu m(2) for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.'));

Abstract: In this work we investigate quantum ballistic transport in ultrasmall junctionless and inversion mode semiconducting nanowire transistors within the framework of the self-consistent Schrödinger-Poisson problem. The quantum transmitting boundary method is used to generate open boundary conditions between the active region and the electron reservoirs. We adopt a subband decomposition approach to make the problem numerically tractable and make a comparison of four different numerical approaches to solve the self-consistent Schrödinger-Poisson problem. Finally we discuss the IV-characteristics for small (r≤5 nm) GaAs nanowire transistors. The novel junctionless pinch-off FET or junctionless nanowire transistor is extensively compared with the gate-all-around (GAA) nanowire MOSFET.

Abstract: Simulation results of electrostatics in Si cylindrical junctionless nanowire transistors with a homogenous channel are presented. Junctionless transistors including strain and arbitrary crystallographic orientations are studied. Size quantization effects are simulated by self-consistent solutions of the Poisson and Schrodinger equations. The 6 x 6 k.p method is employed for the calculation of the valence subband structure in a junctionless nanowire pFET. The influence of stress/strain and crystallographic channel orientation on to the electrostatics in terms of subband structure, charge density, and C-V curve is systematically studied. (C) 2011 Elsevier Ltd. All rights reserved.

Abstract: We study the resistivity scaling in nanometer-sized metallic wires due to surface roughness and grain-boundaries, currently the main cause of electron scattering in nanoscaled interconnects. The resistivity has been obtained with the Boltzmann transport equation, adopting the relaxation time approximation of the distribution function and the effective mass approximation for the conducting electrons. The relaxation times are calculated exactly, using Fermi's golden rule, resulting in a correct relaxation time for every sub-band state contributing to the transport. In general, the relaxation time strongly depends on the sub-band state, something that remained unclear with the methods of previous work. The resistivity scaling is obtained for different roughness and grain-boundary properties, showing large differences in scaling behavior and relaxation times. Our model clearly indicates that the resistivity is dominated by grain-boundary scattering, easily surpassing the surface roughness contribution by a factor of 10. (C) 2014 AIP Publishing LLC.

Abstract: It is generally understood that the resistivity of metal thin films scales with film thickness mainly due to grain boundary and boundary surface scattering. Recently, several experiments and ab initio simulations have demonstrated the impact of crystal orientation on resistivity scaling. The crystal orientation cannot be captured by the commonly used resistivity scaling models and a qualitative understanding of its impact is currently lacking. In this work, we derive a resistivity scaling model that captures grain boundary and boundary surface scattering as well as the anisotropy of the band structure. The model is applied to Cu and Ru thin films, whose conduction bands are (quasi-) isotropic and anisotropic, respectively. After calibrating the anisotropy with ab initio simulations, the resistivity scaling models are compared to experimental resistivity data and a renormalization of the fitted grain boundary reflection coefficient can be identified for textured Ru.

Abstract: In the quantum mechanical simulation of exploratory semiconductor devices, continuum methods based on a k.p/envelope function model have the potential to significantly reduce the computational burden compared to prevalent atomistic methods. However, full-zone k.p/envelope function simulation approaches are scarce and existing implementations are not self-consistent with the calculation of the electrostatic potential due to the lack of a stable procedure and a proper normalization of the multi-band envelope functions. Here, we therefore present a self-consistent procedure based on a full-zone spectral k.p/envelope function band structure model. First, we develop a proper normalization for the multi-band envelope functions in the presence of transmitting boundary conditions. This enables the calculation of the free carrier densities. Next, we construct a procedure to obtain self-consistency of the carrier densities with the electrostatic potential. This procedure is stabilized with an adaptive scheme that relies on the solution of Poisson's equation in the Gummel form, combined with successive underrelaxation. Finally, we apply our procedure to homostructure In0.53Ga0.47As tunnel field-effect transistors (TFETs) and staggered heterostructure GaAs0.5Sb0.5/In0.53Ga0.47As TFETs and show the importance of self-consistency on the device predictions for scaled dimensions. Published by AIP Publishing.