Abstract: This paper benchmarks various epitaxial growth schemes based on n-type group-IV materials as viable source/drain candidates for Ge nMOS devices. Si:P grown at low temperature on Ge, gives an active carrier concentration as high as 3.5 x 10(20) cm(-3) and a contact resistivity down to 7.5 x 10(-9) Omega.cm(2). However, Si:P growth is highly defective due to large lattice mismatch between Si and Ge. Within the material stacks assessed, one option for Ge nMOS source/drain stressors would be to stack Si:P, deposited at contact level, on top of a selectively grown n-SiyGe1-x-ySnx at source/drain level, in line with the concept of Si passivation of n-Ge surfaces to achieve low contact resistivities as reported in literature (Martens et al. 2011 Appl. Phys. Lett., 98, 013 504). The saturation in active carrier concentration with increasing P (or As)-doping is the major bottleneck in achieving low contact resistivities for as-grown Ge or SiyGe1-x-ySnx. We focus on understanding various dopant deactivation mechanisms in P-doped Ge and Ge1-xSnx alloys. First principles simulation results suggest that P deactivation in Ge and Ge1-xSnx can be explained both by P-clustering and donor-vacancy complexes. Positron annihilation spectroscopy analysis, suggests that dopant deactivation in P-doped Ge and Ge1-xSnx is primarily due to the formation of P-n-V and SnmPn-V clusters. (C) 2020 The Author(s). Published on behalf of The Electrochemical Society by IOP Publishing Limited.

Abstract: Si:C and Si:C:P alloys are potential candidates for source-drain stressor applications in n-type Fin Field Effect Transistors (FinFETs). Increasing the C content to achieve high strain results in the arrangement of C atoms as third nearest neighbors (3nn) in the Si: C lattice. During thermal annealing, the presence of C atoms as 3nn may promote clustering at the interstitial sites, causing loss of stress. The concentration of C atoms as 3nn is reduced by the incorporation of a small amount of Ge atoms during the growth, whereas in-situ P doping does not influence this 3nn distribution [J Solid State Sci. Technol vol 6, p 755, 2017]. Small amounts of Ge are provided during low temperature selective epitaxial growth scheme, which are based on cyclic deposition and etching (CDE). In this work, we aim to provide physical insights into the aforementioned phenomena, to understand the behavior of 3nn C atoms and the types of defects that are formed in the annealed Si: C films. Using ab-initio simulations, the Ge-C interaction in the Si matrix is investigated and this insight is used to explain how the Ge incorporation leads to a reduced 3nn distribution of the C atoms. The interaction between C and P in the Si: C: P films is also investigated to explain why the P incorporation has not led to a reduction in the 3nn distribution. We then report on the Raman characterization of Si: C layers subjected to post epi annealing. As the penetration depth of the laser is dependent on the wavelength, Raman measurements at two different wavelengths enable us to probe the depth distribution of 3nn C atoms after applying different annealing conditions. We observed a homogeneous loss in 3nn C throughout the layer. Whereas in the kinematic modeling of high resolution X-ray diffraction spectra, a gradient in the substitutional C loss was observed close to the epitaxial layer/substrate interface. This gradient can be due to the out diffusion of C atoms into the Si substrate or to the formation of interstitial C clusters, which cannot be distinguished in HR-XRD. Deep Level Transient Spectroscopy indicated that the prominent out-diffusing species was interstitial CO complex while the interstitial C defects were also prevalent in the epi layer. (c) 2019 The Electrochemical Society.

Abstract: Heavily P doped Si:P epitaxial layers have gained interest in recent times as a promising source-drain stressor material for n type FinFETs (Fin Field Effect Transistors). They are touted to provide excellent conductivity as well as tensile strain. Although the as-grown layers do provide tensile strain, their conductivity exhibits an unfavorable behavior. It reduces with increasing P concentration (P > 1E21 at/cm(3)), accompanied by a saturation in the active carrier concentration. Subjecting the layers to laser annealing increases the conductivity and activates a fraction of P atoms. However, there is also a concurrent reduction in tensile strain (<1%). Literature proposes the formation of local semiconducting Si3P4 complexes to explain the observed behaviors in Si:P [Z. Ye et al., ECS Trans., 50(9) 2013, p. 1007-10111. The development of tensile strain and the saturation in active carrier is attributed to the presence of local complexes while their dispersal on annealing is attributed to strain reduction and increase in active carrier density. However, the existence of such local complexes is not proven and a fundamental void exists in understanding the structure-property correlation in Si:P films. In this respect, our work investigates the reason behind the evolution of strain and electrical properties in the as-grown and annealed Si:P epitaxial layers using ab-initio techniques and corroborate the results with physical characterization techniques. It will be shown that the strain developed in Si:P films is not due to any specific complexes while the formation of Phosphorus-vacancy complexes will be shown responsible for the carrier saturation and the increase in resistivity in the as-grown films. Interstitial/precipitate formation is suggested to be a reason for the strain loss in the annealed films. (C) The Author(s) 2018. Published by ECS.

Abstract: Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET devices. We use Si4H10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 degrees C. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during the Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions.

Abstract: Crystalline superlattices consisting of alternating periods of Si layers and O-atomic layers are potential new channel materials for scaled CMOS devices. In this letter, we investigate Chemical Vapor Deposition (CVD) for the controlled deposition of O-atoms with O-3 as precursor on Si(100) substrates and Si epitaxy on the O-layer. The O-3 reaction at 50 degrees C on the H-terminated Si results in the formation of Si-OH and/or Si-O-Si-H surface species with monolayer O-content. Defect-free epitaxial growth of Si on an O-layer containing 6.4E+14 O-atoms/cm(2) is achieved from SiH4 at 500 degrees C. (C) 2013 The Electrochemical Society. All rights reserved.