Abstract: We analyze the phenomenon of back hopping in spin-torque induced switching of the magnetization in perpendicularly magnetized tunnel junctions. The analysis is based on single-shot time-resolved conductance measurements of the pulse-induced back hopping. Studying several material variants reveals that the back hopping is a feature of the nominally fixed system of the tunnel junction. The back hopping is found to proceed by two sequential switching events that lead to a final state P' of conductance close to-but distinct from-that of the conventional parallel state. The P' state does not exist at remanence. It generally relaxes to the conventional antiparallel state if the current is removed. The P' state involves a switching of the sole spin-polarizing part of the fixed layers. The analysis of literature indicates that back hopping occurs only when the spin-polarizing layer is too weakly coupled to the rest of the fixed system, which justifies a posteriori the mitigation strategies of back hopping that were implemented empirically in spin-transfer-torque magnetic random access memories.

Abstract: The integration of van der Waals materials in nanoelectronic devices requires the deposition of few-layered MX2 films with excellent quality crystals covering a large area. In recent years, astonishing progress in the monolayer growth of WS2 and MoS2 was demonstrated, but multilayer growth resulted often in separated triangular or hexagonal islands. These polycrystalline films cannot fully employ the specific MX2 properties since they are not connected in-plane to the other domains. To coalesce separated islands, ultrahigh-temperature postdeposition anneals in H2S are applied, which are not compatible with bare silicon substrates. Starting from the deposition of stoichiometric short-ordered films, the present work studies different options for subsequent high-temperature annealing in an inert atmosphere to form crystalline films with large grains from stoichiometric films with small grains. The rapid thermal annealing, performed over a few seconds, is compared to excimer laser annealing in the nanosecond range, which are both able to crystallize the thin WS2. The WS2 recrystallization temperature can be lowered using metallic crystallization promoters (Co and Ni). The best result is obtained using a Co cap, due to the circumvention of Co and S binary phase formation below the eutectic temperature. The recrystallization above a critical temperature is accompanied by sulfur loss and 3D regrowth. These undesired effects can be suppressed by the application of a dielectric capping layer prior to annealing. A SiO2 cap can suppress the sulfur loss successfully during annealing and reveals improved material quality in comparison to noncapped films Published by the AVS.

Abstract: <script type='text/javascript'>document.write(unpmarked('Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality – the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 mu m(2) for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.'));

Abstract: Direct exchange interaction allows spins to be magnetically ordered. Additionally, it can be an efficient manipulation pathway for low-powered spintronic logic devices. We present a novel logic scheme driven by exchange between two distinct regions in a composite magnetic layer containing a bistable canted magnetization configuration. By applying a magnetic field pulse to the input region, the magnetization state is propagated to the output via spin-to-spin interaction in which the output state is given by the magnetization orientation of the output region. The dependence of this scheme with input field conditions is extensively studied through a wide range of micromagnetic simulations. These results allow different logic operating modes to be extracted from the simulation results, and majority logic is successfully demonstrated.

Abstract: A spin wave majority fork-like structure with feature size of 40 nm, is presented and investigated, through micromagnetic simulations. The structure consists of three merging out-of-plane magnetization spin wave buses and four magneto-electric cells serving as three inputs and an output. The information of the logic signals is encoded in the phase of the transmitted spin waves and subsequently stored as direction of magnetization of the magneto-electric cells upon detection. The minimum dimensions of the structure that produce an operational majority gate are identified. For all input combinations, the detection scheme employed manages to capture the majority phase result of the spin wave interference and ignore all reflection effects induced by the geometry of the structure. (C) 2017 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

Abstract: We present a method for area selective deposition of 2D WS2 nanoribbons with tunable thickness on a dielectric substrate. The process is based on a complete conversion of a prepatterned, H-terminated Si layer to metallic W by WF6, followed by in situ sulfidation by H2S. The reaction process, performed at 450 degrees C, yields nanoribbons with lateral dimension down to 20 nm and with random basal plane orientation. The thickness of the nanoribbons is accurately controlled by the thickness of the pre-deposited Si layer. Upon rapid thermal annealing at 900 degrees C under inert gas, the WS2 basal planes align parallel to the substrate.

Abstract: Conventional junctionless (JL) multi/gate (MuG) field-effect transistors (FETs) require extremely scaled channels to deliver high on-state current with low short-channel effect related leakage. In this letter, using ultra-thin 2D materials (e.g., monolayer MoS2), we present comparison of short-channel effects in JL, and inversion-mode (IM) FETs. We show that JL FETs exhibit better sub-threshold slope (S.S.) and drain-induced-barrier-lowering (DIBL) in comparison to IM FETs due to reduced peak electric field at the junctions. But, threshold voltage (VT) roll-off with channel length downscaling is found to be significantly higher in JL FETs than IM FETs, due to higher source/drain controlled charges (dE/dx) in the channel. Further, we show that although VT roll-off in JL FETs improves by increasing the gate control, i.e., by scaling the oxide, or channel thickness, the sensitivity of threshold voltage on structural parameters is found out to be high. (C) 2016 AIP Publishing LLC.