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“Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures”. Loo R, Arimura H, Cott D, Witters L, Pourtois G, Schulze A, Douhard B, Vanherle W, Eneman G, Richard O, Favia P, Mitard J, Mocuta D, Langer R, Collaert N, ECS journal of solid state science and technology 7, P66 (2018). http://doi.org/10.1149/2.0191802JSS
Abstract: Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET and Gate All Around devices. We use Si4H10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 degrees. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions. (C) The Author(s) 2018. Published by ECS.
Keywords: A1 Journal article; Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
Impact Factor: 1.787
Times cited: 5
DOI: 10.1149/2.0191802JSS
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“Titanium (germano-)silicides featuring 10-9 Ω.cm2 contact resistivity and improved compatibility to advanced CMOS technology”. Yu H, Schaekers M, Chew SA, Eyeraert J-L, Dabral A, Pourtois G, Horiguchi N, Mocuta D, Collaert N, De Meyer K, 2018 18th International Workshop On Junction Technology (iwjt) , 80 (2018)
Abstract: uIn this work, we discuss three novel Ti (germano-)silicidation techniques featuring respectively the pre-contact amorphization implantation (PCAI), the TiSi co-deposition, and Ti atomic layer deposition (ALD). All three techniques form TiSix(Ge-y) contacts with ultralow contact resistivity (rho(c)) of (1-3)x10(-9) Omega.cm(2) on both highly doped n-Si and p-SiGe substrates: these techniques meet rho(c) requirement of 5-14 nm CMOS technology and feature unified CMOS contact solutions. We further discuss the compatibility of these techniques to the realistic CMOS transistor fabrication.
Keywords: P1 Proceeding; Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
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“Epitaxial CVD growth of ultra-thin Si passivation layers on strained Ge fin structures”. Loo R, Arimura H, Cott D, Witters L, Pourtois G, Schulze A, Douhard B, Vanherle W, Eneman G, Richard O, Favia P, Mitard J, Mocuta D, Langer R, Collaert N, Semiconductor Process Integration 10 , 241 (2017). http://doi.org/10.1149/08004.0241ECST
Abstract: Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET devices. We use Si4H10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 degrees C. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during the Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions.
Keywords: P1 Proceeding; Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
DOI: 10.1149/08004.0241ECST
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