Abstract: This paper benchmarks various epitaxial growth schemes based on n-type group-IV materials as viable source/drain candidates for Ge nMOS devices. Si:P grown at low temperature on Ge, gives an active carrier concentration as high as 3.5 x 10(20) cm(-3) and a contact resistivity down to 7.5 x 10(-9) Omega.cm(2). However, Si:P growth is highly defective due to large lattice mismatch between Si and Ge. Within the material stacks assessed, one option for Ge nMOS source/drain stressors would be to stack Si:P, deposited at contact level, on top of a selectively grown n-SiyGe1-x-ySnx at source/drain level, in line with the concept of Si passivation of n-Ge surfaces to achieve low contact resistivities as reported in literature (Martens et al. 2011 Appl. Phys. Lett., 98, 013 504). The saturation in active carrier concentration with increasing P (or As)-doping is the major bottleneck in achieving low contact resistivities for as-grown Ge or SiyGe1-x-ySnx. We focus on understanding various dopant deactivation mechanisms in P-doped Ge and Ge1-xSnx alloys. First principles simulation results suggest that P deactivation in Ge and Ge1-xSnx can be explained both by P-clustering and donor-vacancy complexes. Positron annihilation spectroscopy analysis, suggests that dopant deactivation in P-doped Ge and Ge1-xSnx is primarily due to the formation of P-n-V and SnmPn-V clusters. (C) 2020 The Author(s). Published on behalf of The Electrochemical Society by IOP Publishing Limited.

Abstract: Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET devices. We use Si4H10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 degrees C. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during the Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions.

Abstract: Crystalline superlattices consisting of alternating periods of Si layers and O-atomic layers are potential new channel materials for scaled CMOS devices. In this letter, we investigate Chemical Vapor Deposition (CVD) for the controlled deposition of O-atoms with O-3 as precursor on Si(100) substrates and Si epitaxy on the O-layer. The O-3 reaction at 50 degrees C on the H-terminated Si results in the formation of Si-OH and/or Si-O-Si-H surface species with monolayer O-content. Defect-free epitaxial growth of Si on an O-layer containing 6.4E+14 O-atoms/cm(2) is achieved from SiH4 at 500 degrees C. (C) 2013 The Electrochemical Society. All rights reserved.