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Author |
Dutta, S.; Zografos, O.; Gurunarayanan, S.; Radu, I.; Sorée, B.; Catthoor, F.; Naeemi, A. |
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Title |
Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation |
Type |
A1 Journal article |
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Year  |
2017 |
Publication |
Scientific reports |
Abbreviated Journal |
Sci Rep-Uk |
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Volume |
7 |
Issue |
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Pages |
17866 |
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Keywords |
A1 Journal article; Engineering sciences. Technology; Condensed Matter Theory (CMT) |
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Abstract |
<script type='text/javascript'>document.write(unpmarked('Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality – the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 mu m(2) for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.')); |
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Publisher |
Nature Publishing Group |
Place of Publication |
London |
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Wos |
000418359600116 |
Publication Date |
2017-12-13 |
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Edition |
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ISSN |
2045-2322 |
ISBN |
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Additional Links |
UA library record; WoS full record; WoS citing articles |
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Impact Factor |
4.259 |
Times cited |
2 |
Open Access |
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Notes |
; ; |
Approved |
Most recent IF: 4.259 |
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Call Number |
UA @ lucian @ c:irua:148514 |
Serial |
4891 |
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Author |
Doevenspeck, J.; Zografos, O.; Gurunarayanan, S.; Lauwereins, R.; Raghavan, P.; Sorée, B. |
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Title |
Design and simulation of plasmonic interference-based majority gate |
Type |
A1 Journal article |
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Year |
2017 |
Publication |
AIP advances |
Abbreviated Journal |
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Volume |
7 |
Issue |
6 |
Pages |
065116 |
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Keywords |
A1 Journal article; Engineering sciences. Technology; Condensed Matter Theory (CMT) |
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Abstract |
Major obstacles in current CMOS technology, such as the interconnect bottleneck and thermal heat management, can be overcome by employing subwavelength-scaled light in plasmonic waveguides and devices. In this work, a plasmonic structure that implements the majority (MAJ) gate function is designed and thoroughly studied through simulations. The structure consists of three merging waveguides, serving as the MAJ gate inputs. The information of the logic signals is encoded in the phase of transmitted surface plasmon polaritons (SPP). SPPs are excited at all three inputs and the phase of the output SPP is determined by theMAJof the input phases. The operating dimensions are identified and the functionality is verified for all input combinations. This is the first reported simulation of a plasmonic MAJ gate and thus contributes to the field of optical computing at the nanoscale. (C) 2017 Author(s). |
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Wos |
000404621200036 |
Publication Date |
2017-06-23 |
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Series Volume |
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Series Issue |
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Edition |
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ISSN |
2158-3226 |
ISBN |
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Additional Links |
UA library record; WoS full record; WoS citing articles |
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Impact Factor |
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Times cited |
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Open Access |
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Notes |
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Approved |
no |
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Call Number |
UA @ admin @ c:irua:152632 |
Serial |
7764 |
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