Abstract: Over the past few decades, superconducting circuits have been used to realize various novel electronic devices such as quantum bits, SQUIDs, parametric amplifiers, etc. One domain, however, where superconducting circuits fall short is information storage. Superconducting memories are based on the quantization of magnetic flux in superconducting loops. Standard implementations store information as magnetic flux quanta in a superconducting loop interrupted by two Josephson junctions (i.e., a SQUID). However, due to the large inductance required, the size of the SQUID loop cannot be scaled below several micrometers, resulting in low-density memory chips. Here, we propose a scalable memory consisting of a voltage-biased superconducting ring threaded by a half-quantum flux bias. By numerically solving the time-dependent Ginzburg-Landau equations, we show that applying a time-dependent bias voltage in the microwave range constitutes a writing mechanism to change the number of stored flux quanta within the ring. Since the proposed device does not require a large loop inductance, it can be scaled down, enabling a high-density memory technology. (C) 2019 Author(s).

Abstract: In tunnel field-effect transistors, trap-assisted tunneling (TAT) is one of the probable causes for degraded subthreshold swing. The accurate quantum-mechanical (QM) assessment of TAT currents also requires a QM treatment of phonon-assisted tunneling (PAT) currents. Therefore, we present a multi-band PAT current formalism within the framework of the quantum transmitting boundary method. An envelope function approximation is used to construct the electron-phonon coupling terms corresponding to local Frohlich-based phonon-assisted inter-band tunneling in direct-bandgap III-V semiconductors. The PAT current density is studied in up to 100 nm long and 20 nm wide p-n diodes with the 2- and 15-band material description of our formalism. We observe an inefficient electron-phonon coupling across the tunneling junction. We further demonstrate the dependence of PAT currents on the device length, for our non-self-consistent formalism which neglects changes in the electron distribution function caused by the electron-phonon coupling. Finally, we discuss the differences in doping dependence between direct band-to-band tunneling and PAT current. Published under license by AIP Publishing.

Abstract: A spin wave majority fork-like structure with feature size of 40 nm, is presented and investigated, through micromagnetic simulations. The structure consists of three merging out-of-plane magnetization spin wave buses and four magneto-electric cells serving as three inputs and an output. The information of the logic signals is encoded in the phase of the transmitted spin waves and subsequently stored as direction of magnetization of the magneto-electric cells upon detection. The minimum dimensions of the structure that produce an operational majority gate are identified. For all input combinations, the detection scheme employed manages to capture the majority phase result of the spin wave interference and ignore all reflection effects induced by the geometry of the structure. (C) 2017 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

Abstract: Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In0.53Ga0.47As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET. (C) 2015 AIP Publishing LLC.

Abstract: Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kane's formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In0.53Ga0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In0.53Ga0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance compared to MOSFET.

Abstract: Group IV based tunnel field-effect transistors generally show lower on-current than III-V based devices because of the weaker phonon-assisted tunneling transitions in the group IV indirect bandgap materials. Direct tunneling in Ge, however, can be enhanced by strain engineering. In this work, we use a 30-band k.p method to calculate the band structure of biaxial tensile strained Ge and then extract the bandgaps and effective masses at Gamma and L symmetry points in k-space, from which the parameters for the direct and indirect band-to-band tunneling (BTBT) models are determined. While transitions from the heavy and light hole valence bands to the conduction band edge at the L point are always bridged by phonon scattering, we highlight a new finding that only the light-holelike valence band is strongly coupling to the conduction band at the Gamma point even in the presence of strain based on the 30-band k.p analysis. By utilizing a Technology Computer Aided Design simulator equipped with the calculated band-to-band tunneling BTBT models, the electrical characteristics of tensile strained Ge point and line tunneling devices are self-consistently computed considering multiple dynamic nonlocal tunnel paths. The influence of field-induced quantum confinement on the tunneling onset is included. Our simulation predicts that an on-current up to 160 (260) mu A/mu m can be achieved along with on/off ratio > 10(6) for V-DD = 0.5V by the n-type (p-type) line tunneling device made of 2.5% biaxial tensile strained Ge. (C) 2014 AIP Publishing LLC.

Abstract: A figure of merit I60 is proposed for sub-60 mV/decade devices as the highest current where the input characteristics exhibit a transition from sub- to super-60 mV/decade behavior. For sub-60 mV/decade devices to be competitive with metal-oxide-semiconductor field-effect devices, I60 has to be in the 1-10 μA/μm range. The best experimental tunnel field-effect transistors (TFETs) in the literature only have an I60 of 6×10-3 μA/μm but using theoretical simulations, we show that an I60 of up to 10 μA/μm should be attainable. It is proven that the Schottky barrier FET (SBFET) has a 60 mV/decade subthreshold swing limit while combining a SBFET and a TFET does improve performance.

Abstract: A general framework to calculate the Zener current in an indirect semiconductor with an externally applied potential is provided. Assuming a parabolic valence and conduction band dispersion, the semiconductor is in equilibrium in the presence of the external field as long as the electron-phonon interaction is absent. The linear response to the electron-phonon interaction results in a non-equilibrium system. The Zener tunneling current is calculated from the number of electrons making the transition from valence to conduction band per unit time. A convenient expression based on the single particle spectral functions is provided, enabling the evaluation of the Zener tunneling current under any three-dimensional potential profile. For a one-dimensional potential profile an analytical expression is obtained for the current in a bulk semiconductor, a semiconductor under uniform field, and a semiconductor under a non-uniform field using the WKB (Wentzel-Kramers-Brillouin) approximation. The obtained results agree with the Kane result in the low field limit. A numerical example for abrupt p-n diodes with different doping concentrations is given, from which it can be seen that the uniform field model is a better approximation than the WKB model, but a direct numerical treatment is required for low bias conditions.

Abstract: The capacitance-voltage (C-V) characteristic is calculated for p-type In_0.53Ga_0.47As metal-oxide-semiconductor (MOS) structures based on a self-consistent PoissonSchrödinger solution. For strong inversion, charge quantization leads to occupation of the satellite valleys which appears as a sharp increase in the capacitance toward the oxide capacitance. The results indicate that the charge quantization, even in the absence of interface defects (D_it), is a contributing factor to the experimental observation of an almost symmetric C-V response for In_0.53Ga_0.47As MOS structures. In addition, nonparabolic corrections are shown to enhance the depopulation of the Γ valley, shifting the capacitance increase to lower inversion charge densities.

Abstract: Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.

Abstract: In this study we investigate the effect of device topology on the ballistic current in n-channel metal-oxide-semiconductor field-effect transistors. Comparison of the nanoscale planar and double-gate devices reveals that, down to a certain thickness of the double gate film, the ballistic current flowing in the double gate device is twice as large compared to its planar counterpart. On the other hand, further thinning of the film beyond this threshold is found to change noticeably the confinement and transport characteristics, which are strongly depending on the film material and the surface orientation. For double gate Ge and Si devices there exists a critical film thickness below which the transverse gate field is no longer effectively screened by the inversion layer electron gas and mutual inversion of the two gates is turned on. In the case of GaAs and other similar IIIV compounds, a decrease in the film thickness may drastically change the occupation of the L-valleys and therefore amend the transport properties. The simulation results show that, in both cases, the ballistic current and the transconductance are considerably enhanced.

Abstract: The effects of thermal annealing in inert Ar gas atmosphere of SiO2-supported, exfoliated single-layer graphene are investigated in this work. A systematic, reproducible change in the electronic properties of graphene is observed after annealing. The most prominent Raman features in graphene, the G and 2D peaks, change in accord to what is expected in the case of hole doping. The results of electrical characterization performed on annealed, back-gated field-effect graphene devices show that the neutrality point voltage VNP increases monotonically with the annealing temperature, confirming the occurrence of excess hole accumulation. No degradation of the structural properties of graphene is observed after annealing at temperatures as high as 400 °C. Thermal annealing of single-layer graphene in controlled Ar atmosphere can therefore be considered a technique to reproducibly modify the electronic structure of graphene by tuning its Fermi level.

Abstract: We compare the image-force barrier lowering (IFBL) and calculate the resulting contact resistance for four different metal-dielectric-two-dimensional (2D) material configurations. We analyze edge contacts in three different geometries (a homogeneous dielectric throughout, including the 2D layer; a homogeneous dielectric surrounding the 2D layer, both ungated and back gated) and also a top-contact assuming a homogeneous dielectric. The image potential energy of each configuration is determined and added to the Schottky energy barrier which is calculated assuming a textbook Schottky potential. For each configuration, the contact resistivity is calculated using the WKB approximation and the effective mass approximation using either SiO2 or HfO2 as the surrounding dielectric. We obtain the lowest contact resistance of 1 k Omega mu m by n-type doping an edge contacted transition metal-dichalcogenide (TMD) monolayer, sandwiched between SiO2 dielectric, with similar to 1012 cm-2 donor atoms. When this optimal configuration is used, the contact resistance is lowered by a factor of 50 compared to the situation when the IFBL is not considered.

Abstract: We develop an analytical model for a tunnel field-effect transistor (TFET) with a tilted source junction angle. The tunnel current is derived by using circular tunnel paths along the electric field. The analytical model predicts that a smaller junction angle improves the TFET performance, which is supported by device simulations. An analysis is also made based on straight tunnel paths and tunnel paths corresponding to the trajectory of a classical particle. In all the aforementioned cases, the same conclusions are obtained. A TFET configuration with an encroaching polygon source junction is studied to analyze the junction angle dependence at the smallest junction angles. The improvement of the subthreshold swing (SS) with decreasing junction angle can be achieved by using thinner effective oxide thickness, smaller band gap material and longer encroaching length of the encroaching junction. A TFET with a smaller junction angle on the source side also has an innate immunity against the degradation of the fringing field from the gate electrode via a high-k spacer. A large junction angle on the drain side can suppress the unwanted ambipolar current of TFETs. (c) 2011 Elsevier Ltd. All rights reserved.