Abstract: Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET and Gate All Around devices. We use Si4H10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 degrees. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions. (C) The Author(s) 2018. Published by ECS.

Abstract: The fabrication and integration of low-resistance carbon nanotubes (CNTs) for interconnects in future integrated circuits requires characterization techniques providing structural and electrical information at the nanometer scale. In this paper we present a slice-and-view approach based on electrical atomic force microscopy. Material removal achieved by successive scanning using doped ultra-sharp full-diamond probes, manufactured in-house, enables us to acquire two-dimensional (2D) resistance maps originating from different depths (equivalently different CNT lengths) on CNT-based interconnects. Stacking and interpolating these 2D resistance maps results in a three-dimensional (3D) representation (tomogram). This allows insight from a structural (e.g. size, density, distribution, straightness) and electrical point of view simultaneously. By extracting the resistance evolution over the length of an individual CNT we derive quantitative information about the resistivity and the contact resistance between the CNT and bottom electrode.