| Records |
| Author |
Agarwal, T.; Sorée, B.; Radu, I.; Raghavan, P.; Fiori, G.; Iannaccone, G.; Thean, A.; Heyns, M.; Dehaene, W. |
| Title |
Comparison of short-channel effects in monolayer MoS2 based junctionless and inversion-mode field-effect transistors |
Type |
A1 Journal article |
Year  |
2016 |
Publication |
Applied physics letters |
Abbreviated Journal |
Appl Phys Lett |
| Volume |
108 |
Issue |
108 |
Pages |
023506 |
| Keywords |
A1 Journal article; Condensed Matter Theory (CMT) |
| Abstract |
Conventional junctionless (JL) multi/gate (MuG) field-effect transistors (FETs) require extremely scaled channels to deliver high on-state current with low short-channel effect related leakage. In this letter, using ultra-thin 2D materials (e.g., monolayer MoS2), we present comparison of short-channel effects in JL, and inversion-mode (IM) FETs. We show that JL FETs exhibit better sub-threshold slope (S.S.) and drain-induced-barrier-lowering (DIBL) in comparison to IM FETs due to reduced peak electric field at the junctions. But, threshold voltage (VT) roll-off with channel length downscaling is found to be significantly higher in JL FETs than IM FETs, due to higher source/drain controlled charges (dE/dx) in the channel. Further, we show that although VT roll-off in JL FETs improves by increasing the gate control, i.e., by scaling the oxide, or channel thickness, the sensitivity of threshold voltage on structural parameters is found out to be high. (C) 2016 AIP Publishing LLC. |
| Address |
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| Corporate Author |
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Thesis |
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| Publisher |
American Institute of Physics |
Place of Publication |
New York, N.Y. |
Editor |
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| Language |
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Wos |
000370258400056 |
Publication Date |
2016-01-16 |
| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
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| ISSN |
0003-6951; 1077-3118 |
ISBN |
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Additional Links |
UA library record; WoS full record; WoS citing articles |
| Impact Factor |
3.411 |
Times cited |
13 |
Open Access |
|
| Notes |
; ; |
Approved |
Most recent IF: 3.411 |
| Call Number |
UA @ lucian @ c:irua:132318 |
Serial |
4152 |
| Permanent link to this record |
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| |
| Author |
Katti, G.; Stucchi, M.; Velenis, D.; Sorée, B.; de Meyer, K.; Dehaene, W. |
| Title |
Temperature-dependent modeling and characterization of through-silicon via capacitance |
Type |
A1 Journal article |
| Year |
2011 |
Publication |
IEEE electron device letters |
Abbreviated Journal |
Ieee Electr Device L |
| Volume |
32 |
Issue |
4 |
Pages |
563-565 |
| Keywords |
A1 Journal article; Condensed Matter Theory (CMT) |
| Abstract |
A semianalytical model of the through-silicon via (TSV) capacitance for elevated operating temperatures is derived and verified with electrical measurements. The effect of temperature on the increase in TSV capacitance over different technology parameters is explored, and it is shown that higher oxide thickness reduces the impact of temperature rise on TSV capacitance, while with low doped substrates, which are instrumental for reducing the TSV capacitance, the sensitivity of TSV capacitance to temperature is large and cannot be ignored. |
| Address |
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| Corporate Author |
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Thesis |
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| Publisher |
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Place of Publication |
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Editor |
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| Language |
|
Wos |
000288664800045 |
Publication Date |
2011-03-04 |
| Series Editor |
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Series Title |
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Abbreviated Series Title |
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| Series Volume |
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Series Issue |
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Edition |
|
| ISSN |
0741-3106;1558-0563; |
ISBN |
|
Additional Links |
UA library record; WoS full record; WoS citing articles |
| Impact Factor |
3.048 |
Times cited |
27 |
Open Access |
|
| Notes |
; ; |
Approved |
Most recent IF: 3.048; 2011 IF: 2.849 |
| Call Number |
UA @ lucian @ c:irua:89402 |
Serial |
3498 |
| Permanent link to this record |
