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“Exchange-driven magnetic logic”. Zografos O, Manfrini M, Vaysset A, Sorée B, Ciubotaru F, Adelmann C, Lauwereins R, Raghavan P, Radu IP, Scientific reports 7, 12154 (2017). http://doi.org/10.1038/S41598-017-12447-8
Abstract: Direct exchange interaction allows spins to be magnetically ordered. Additionally, it can be an efficient manipulation pathway for low-powered spintronic logic devices. We present a novel logic scheme driven by exchange between two distinct regions in a composite magnetic layer containing a bistable canted magnetization configuration. By applying a magnetic field pulse to the input region, the magnetization state is propagated to the output via spin-to-spin interaction in which the output state is given by the magnetization orientation of the output region. The dependence of this scheme with input field conditions is extensively studied through a wide range of micromagnetic simulations. These results allow different logic operating modes to be extracted from the simulation results, and majority logic is successfully demonstrated.
Keywords: A1 Journal article; Engineering sciences. Technology; Condensed Matter Theory (CMT)
Impact Factor: 4.259
Times cited: 7
DOI: 10.1038/S41598-017-12447-8
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“Design and simulation of plasmonic interference-based majority gate”. Doevenspeck J, Zografos O, Gurunarayanan S, Lauwereins R, Raghavan P, Sorée B, AIP advances 7, 065116 (2017). http://doi.org/10.1063/1.4989817
Abstract: Major obstacles in current CMOS technology, such as the interconnect bottleneck and thermal heat management, can be overcome by employing subwavelength-scaled light in plasmonic waveguides and devices. In this work, a plasmonic structure that implements the majority (MAJ) gate function is designed and thoroughly studied through simulations. The structure consists of three merging waveguides, serving as the MAJ gate inputs. The information of the logic signals is encoded in the phase of transmitted surface plasmon polaritons (SPP). SPPs are excited at all three inputs and the phase of the output SPP is determined by theMAJof the input phases. The operating dimensions are identified and the functionality is verified for all input combinations. This is the first reported simulation of a plasmonic MAJ gate and thus contributes to the field of optical computing at the nanoscale. (C) 2017 Author(s).
Keywords: A1 Journal article; Engineering sciences. Technology; Condensed Matter Theory (CMT)
DOI: 10.1063/1.4989817
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“Non-volatile spin wave majority gate at the nanoscale”. Zografos O, Dutta S, Manfrini M, Vaysset A, Sorée B, Naeemi A, Raghavan P, Lauwereins R, Radu IP, AIP advances
T2 –, 61st Annual Conference on Magnetism and Magnetic Materials (MMM), OCT 31-NOV 04, 2016, New Orleans, LA 7, 056020 (2017). http://doi.org/10.1063/1.4975693
Abstract: A spin wave majority fork-like structure with feature size of 40 nm, is presented and investigated, through micromagnetic simulations. The structure consists of three merging out-of-plane magnetization spin wave buses and four magneto-electric cells serving as three inputs and an output. The information of the logic signals is encoded in the phase of the transmitted spin waves and subsequently stored as direction of magnetization of the magneto-electric cells upon detection. The minimum dimensions of the structure that produce an operational majority gate are identified. For all input combinations, the detection scheme employed manages to capture the majority phase result of the spin wave interference and ignore all reflection effects induced by the geometry of the structure. (C) 2017 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
Keywords: A1 Journal article; Engineering sciences. Technology; Condensed Matter Theory (CMT)
Impact Factor: 1.568
Times cited: 13
DOI: 10.1063/1.4975693
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“Comparison of short-channel effects in monolayer MoS2 based junctionless and inversion-mode field-effect transistors”. Agarwal T, Sorée B, Radu I, Raghavan P, Fiori G, Iannaccone G, Thean A, Heyns M, Dehaene W, Applied physics letters 108, 023506 (2016). http://doi.org/10.1063/1.4939933
Abstract: Conventional junctionless (JL) multi/gate (MuG) field-effect transistors (FETs) require extremely scaled channels to deliver high on-state current with low short-channel effect related leakage. In this letter, using ultra-thin 2D materials (e.g., monolayer MoS2), we present comparison of short-channel effects in JL, and inversion-mode (IM) FETs. We show that JL FETs exhibit better sub-threshold slope (S.S.) and drain-induced-barrier-lowering (DIBL) in comparison to IM FETs due to reduced peak electric field at the junctions. But, threshold voltage (VT) roll-off with channel length downscaling is found to be significantly higher in JL FETs than IM FETs, due to higher source/drain controlled charges (dE/dx) in the channel. Further, we show that although VT roll-off in JL FETs improves by increasing the gate control, i.e., by scaling the oxide, or channel thickness, the sensitivity of threshold voltage on structural parameters is found out to be high. (C) 2016 AIP Publishing LLC.
Keywords: A1 Journal article; Condensed Matter Theory (CMT)
Impact Factor: 3.411
Times cited: 13
DOI: 10.1063/1.4939933
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