Abstract: Group IV based tunnel field-effect transistors generally show lower on-current than III-V based devices because of the weaker phonon-assisted tunneling transitions in the group IV indirect bandgap materials. Direct tunneling in Ge, however, can be enhanced by strain engineering. In this work, we use a 30-band k.p method to calculate the band structure of biaxial tensile strained Ge and then extract the bandgaps and effective masses at Gamma and L symmetry points in k-space, from which the parameters for the direct and indirect band-to-band tunneling (BTBT) models are determined. While transitions from the heavy and light hole valence bands to the conduction band edge at the L point are always bridged by phonon scattering, we highlight a new finding that only the light-holelike valence band is strongly coupling to the conduction band at the Gamma point even in the presence of strain based on the 30-band k.p analysis. By utilizing a Technology Computer Aided Design simulator equipped with the calculated band-to-band tunneling BTBT models, the electrical characteristics of tensile strained Ge point and line tunneling devices are self-consistently computed considering multiple dynamic nonlocal tunnel paths. The influence of field-induced quantum confinement on the tunneling onset is included. Our simulation predicts that an on-current up to 160 (260) mu A/mu m can be achieved along with on/off ratio > 10(6) for V-DD = 0.5V by the n-type (p-type) line tunneling device made of 2.5% biaxial tensile strained Ge. (C) 2014 AIP Publishing LLC.

Abstract: We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher ON-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement (QC). It is shown that the two disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by placing a counter-doped parallel pocket underneath the gate-source overlap. The pocket also significantly reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-on-source-only tunnel field-effect transistor simulations.

Abstract: We develop an analytical model for a tunnel field-effect transistor (TFET) with a tilted source junction angle. The tunnel current is derived by using circular tunnel paths along the electric field. The analytical model predicts that a smaller junction angle improves the TFET performance, which is supported by device simulations. An analysis is also made based on straight tunnel paths and tunnel paths corresponding to the trajectory of a classical particle. In all the aforementioned cases, the same conclusions are obtained. A TFET configuration with an encroaching polygon source junction is studied to analyze the junction angle dependence at the smallest junction angles. The improvement of the subthreshold swing (SS) with decreasing junction angle can be achieved by using thinner effective oxide thickness, smaller band gap material and longer encroaching length of the encroaching junction. A TFET with a smaller junction angle on the source side also has an innate immunity against the degradation of the fringing field from the gate electrode via a high-k spacer. A large junction angle on the drain side can suppress the unwanted ambipolar current of TFETs. (c) 2011 Elsevier Ltd. All rights reserved.

Abstract: A semianalytical model of the through-silicon via (TSV) capacitance for elevated operating temperatures is derived and verified with electrical measurements. The effect of temperature on the increase in TSV capacitance over different technology parameters is explored, and it is shown that higher oxide thickness reduces the impact of temperature rise on TSV capacitance, while with low doped substrates, which are instrumental for reducing the TSV capacitance, the sensitivity of TSV capacitance to temperature is large and cannot be ignored.

Abstract: In this paper we investigate the basic physics of charge carriers (electrons) leaking out of the inversion layer of a metal-oxide-semiconductor capacitor with a biased gate. In particular, we treat the gate leakage current as resulting from two combined processes: (1) the time-dependent decay of electron wave packets representing the inversion-layer charge and (2) the local generation of new electrons replacing those that have leaked away. As a result, the gate current simply emerges as the ratio of the total charge in the inversion layer to the tunneling lifetime. The latter is extracted from the quantum dynamics of the decaying wave packets, while the generation rate is incorporated as a phenomenological source term in the continuity equation. Not only do the gate currents calculated with this model agree very well with experiment, the model also provides an onset to solve the paradox of the current-free bound states representing the resonances of the Schrödinger equation that governs the fully coupled metal-oxide-semiconductor system.

Abstract: The electron wave functions in the inversion layer are analyzed in the case where the dielectric barriers are not infinite. This forces the electron concentration closer to the interface silicon/oxide and reduces the subband energy. This treatment of the inversion layer is extended to the calculation of the electron mobility degradation due to remote Coulomb scattering on a high-k dielectric stacked transistor. The subband energy reduction leads to a decrease of the scattering charge needed to explain the experimental results. This model can also fit better the experimental data when compared with the case where no barrier permeation is considered.