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“Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study”. Lu AKA, Pourtois G, Agarwal T, Afzalian A, Radu IP, Houssa M, Applied physics letters 108, 043504 (2016). http://doi.org/10.1063/1.4940685
Abstract: The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, and sets the limit of the scaling in future transistor designs. (C) 2016 AIP Publishing LLC.
Keywords: A1 Journal article; Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
Impact Factor: 3.411
Times cited: 4
DOI: 10.1063/1.4940685
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“Comparison of short-channel effects in monolayer MoS2 based junctionless and inversion-mode field-effect transistors”. Agarwal T, Sorée B, Radu I, Raghavan P, Fiori G, Iannaccone G, Thean A, Heyns M, Dehaene W, Applied physics letters 108, 023506 (2016). http://doi.org/10.1063/1.4939933
Abstract: Conventional junctionless (JL) multi/gate (MuG) field-effect transistors (FETs) require extremely scaled channels to deliver high on-state current with low short-channel effect related leakage. In this letter, using ultra-thin 2D materials (e.g., monolayer MoS2), we present comparison of short-channel effects in JL, and inversion-mode (IM) FETs. We show that JL FETs exhibit better sub-threshold slope (S.S.) and drain-induced-barrier-lowering (DIBL) in comparison to IM FETs due to reduced peak electric field at the junctions. But, threshold voltage (VT) roll-off with channel length downscaling is found to be significantly higher in JL FETs than IM FETs, due to higher source/drain controlled charges (dE/dx) in the channel. Further, we show that although VT roll-off in JL FETs improves by increasing the gate control, i.e., by scaling the oxide, or channel thickness, the sensitivity of threshold voltage on structural parameters is found out to be high. (C) 2016 AIP Publishing LLC.
Keywords: A1 Journal article; Condensed Matter Theory (CMT)
Impact Factor: 3.411
Times cited: 13
DOI: 10.1063/1.4939933
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