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Author |
Kao, K.-H.; Verhulst, A.S.; Vandenberghe, W.G.; Sorée, B.; Magnus, W.; Leonelli, D.; Groeseneken, G.; De Meyer, K. |
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Title |
Optimization of gate-on-source-only tunnel FETs with counter-doped pockets |
Type |
A1 Journal article |
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Year  |
2012 |
Publication |
IEEE transactions on electron devices |
Abbreviated Journal |
Ieee T Electron Dev |
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Volume |
59 |
Issue |
8 |
Pages |
2070-2077 |
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Keywords |
A1 Journal article; Condensed Matter Theory (CMT) |
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Abstract |
We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher ON-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement (QC). It is shown that the two disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by placing a counter-doped parallel pocket underneath the gate-source overlap. The pocket also significantly reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-on-source-only tunnel field-effect transistor simulations. |
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Place of Publication |
New York, N.Y. |
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Wos |
000306920200011 |
Publication Date |
2012-06-27 |
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Edition |
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ISSN |
0018-9383;1557-9646; |
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Additional Links |
UA library record; WoS full record; WoS citing articles |
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Impact Factor |
2.605 |
Times cited |
72 |
Open Access |
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Notes |
; Manuscript received February 17, 2012; revised May 7, 2012; accepted May 11, 2012. Date of publication June 26, 2012; date of current version July 19, 2012. This work was supported by the Interuniversity Microelectronics Center's Industrial Affiliation Program. The work of W. G. Vandenberghe was supported by the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT-Vlaanderen) through a Ph.D. stipend. The review of this paper was arranged by Editor H. S. Momose. ; |
Approved |
Most recent IF: 2.605; 2012 IF: 2.062 |
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Call Number |
UA @ lucian @ c:irua:100820 |
Serial |
2487 |
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Author |
Verhulst, A.; Sorée, B.; Leonelli, D.; Vandenberghe, W.G.; Groeseneken, G. |
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Title |
Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor |
Type |
A1 Journal article |
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Year |
2010 |
Publication |
Journal Of Applied Physics |
Abbreviated Journal |
J Appl Phys |
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Volume |
107 |
Issue |
2 |
Pages |
024518,1-024518,8 |
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Keywords |
A1 Journal article; Electron Microscopy for Materials Science (EMAT); |
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Abstract |
Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data. |
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Publisher |
American Institute of Physics |
Place of Publication |
New York, N.Y. |
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Wos |
000274180600122 |
Publication Date |
2010-01-28 |
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Edition |
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ISSN |
0021-8979; |
ISBN |
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Additional Links |
UA library record; WoS full record; WoS citing articles |
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Impact Factor |
2.068 |
Times cited |
150 |
Open Access |
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Notes |
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Approved |
Most recent IF: 2.068; 2010 IF: 2.079 |
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Call Number |
UA @ lucian @ c:irua:89507 |
Serial |
2146 |
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