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“A new method to calculate leakage current and its applications for sub-45nm MOSFETs”. Lujan GS, Magnus W, Soree B, Pourghaderi MA, Veloso A, van Dal MJH, Lauwers A, Kubicek S, De Gendt S, Heyns M, De Meyer K, Solid-State Device Research (ESSDERC), European Conference
T2 – ESSDERC 2005 : proceedings of 35th European Solid-State Device Research Conference, September 12-16, 2005, Grenoble, France. Ieee, S.l., page 489 (2005).
Abstract: This paper proposes a new quantum mechanical model for the calculation of leakage currents. The model incorporates both variational calculus and the transfer matrix method to compute the subband energies and the life times of the inversion layer states. The use of variational calculus simplifies the subband energy calculation due to the analytical firm of the wave functions, which offers an attractive perspective towards the calculation of the electron mobility in the channel. The model can be extended to high-k dielectrics with several layers. Good agreement between experimental data and simulation results is obtained for metal gate capacitors.
Keywords: H1 Book chapter; Condensed Matter Theory (CMT)
DOI: 10.1109/ESSDER.2005.1546691
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“Electron relaxation times and resistivity in metallic nanowires due to tilted grain boundary planes”. Moors K, Soree B, Tokei Z, Magnus W, On Ultimate Integration On Silicon (eurosoi-ulis) , 201 (2015)
Abstract: We calculate the resistivity contribution of tilted grain boundaries with varying parameters in sub-10nm diameter metallic nanowires. The results have been obtained with the Boltzmann transport equation and Fermi's golden rule, retrieving correct state-dependent relaxation times. The standard approximation schemes for the relaxation times are shown to fail when grain boundary tilt is considered. Grain boundaries tilted under the same angle or randomly tilted induce a resistivity decrease.
Keywords: P1 Proceeding; Condensed Matter Theory (CMT)
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