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“Non-volatile spin wave majority gate at the nanoscale”. Zografos O, Dutta S, Manfrini M, Vaysset A, Sorée B, Naeemi A, Raghavan P, Lauwereins R, Radu IP, AIP advances
T2 –, 61st Annual Conference on Magnetism and Magnetic Materials (MMM), OCT 31-NOV 04, 2016, New Orleans, LA 7, 056020 (2017). http://doi.org/10.1063/1.4975693
Abstract: A spin wave majority fork-like structure with feature size of 40 nm, is presented and investigated, through micromagnetic simulations. The structure consists of three merging out-of-plane magnetization spin wave buses and four magneto-electric cells serving as three inputs and an output. The information of the logic signals is encoded in the phase of the transmitted spin waves and subsequently stored as direction of magnetization of the magneto-electric cells upon detection. The minimum dimensions of the structure that produce an operational majority gate are identified. For all input combinations, the detection scheme employed manages to capture the majority phase result of the spin wave interference and ignore all reflection effects induced by the geometry of the structure. (C) 2017 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
Keywords: A1 Journal article; Engineering sciences. Technology; Condensed Matter Theory (CMT)
Impact Factor: 1.568
Times cited: 13
DOI: 10.1063/1.4975693
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“Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation”. Dutta S, Zografos O, Gurunarayanan S, Radu I, Sorée B, Catthoor F, Naeemi A, Scientific reports 7, 17866 (2017). http://doi.org/10.1038/S41598-017-17954-2
Abstract: <script type='text/javascript'>document.write(unpmarked('Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality – the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 mu m(2) for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.'));
Keywords: A1 Journal article; Engineering sciences. Technology; Condensed Matter Theory (CMT)
Impact Factor: 4.259
Times cited: 2
DOI: 10.1038/S41598-017-17954-2
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