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“Optimization of gate-on-source-only tunnel FETs with counter-doped pockets”. Kao K-H, Verhulst AS, Vandenberghe WG, Sorée B, Magnus W, Leonelli D, Groeseneken G, De Meyer K, IEEE transactions on electron devices 59, 2070 (2012). http://doi.org/10.1109/TED.2012.2200489
Abstract: We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher ON-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement (QC). It is shown that the two disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by placing a counter-doped parallel pocket underneath the gate-source overlap. The pocket also significantly reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-on-source-only tunnel field-effect transistor simulations.
Keywords: A1 Journal article; Condensed Matter Theory (CMT)
Impact Factor: 2.605
Times cited: 72
DOI: 10.1109/TED.2012.2200489
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“Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor”. Verhulst A, Sorée B, Leonelli D, Vandenberghe WG, Groeseneken G, Journal Of Applied Physics 107, 024518 (2010). http://doi.org/10.1063/1.3277044
Abstract: Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.
Keywords: A1 Journal article; Electron Microscopy for Materials Science (EMAT);
Impact Factor: 2.068
Times cited: 150
DOI: 10.1063/1.3277044
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“Modeling of inter-ribbon tunneling in graphene”. Van de Put ML, Vandenberghe WG, Magnus W, Sorée B, Fischetti MV, 18th International Workshop On Computational Electronics (iwce 2015) (2015)
Abstract: The tunneling current between two crossed graphene ribbons is described invoking the empirical pseudopotential approximation and the Bardeen transfer Hamiltonian method. Results indicate that the density of states is the most important factor determining the tunneling current between small (similar to nm) ribbons. The quasi-one dimensional nature of graphene nanoribbons is shown to result in resonant tunneling.
Keywords: P1 Proceeding; Condensed Matter Theory (CMT)
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