Abstract: The cleaning of two-dimensional (2D) materials is an essential step in the fabrication of future devices, leveraging their unique physical, optical, and chemical properties. Part of these emerging 2D materials are transition metal dichalcogenides (TMDs). So far there is limited understanding of the cleaning of “monolayer” TMD materials. In this study, we report on the use of downstream H₂plasma to clean the surface of monolayer WS₂grown by MOCVD. We demonstrate that high-temperature processing is essential, allowing to maximize the removal rate of polymers and to mitigate damage caused to the WS₂in the form of sulfur vacancies. We show that low temperature in situ carbonyl sulfide (OCS) soak is an efficient way to resulfurize the material, besides high-temperature H₂S annealing. The cleaning processes and mechanisms elucidated in this work are tested on back-gated field-effect transistors, confirming that transport properties of WS₂devices can be maintained by the combination of H₂plasma cleaning and OCS restoration. The low-damage plasma cleaning based on H₂and OCS is very reproducible, fast (completed in a few minutes) and uses a 300 mm industrial plasma etch system qualified for standard semiconductor pilot production. This process is, therefore, expected to enable the industrial scale-up of 2D-based devices, co-integrated with silicon technology.

Abstract: Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kane's formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In0.53Ga0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In0.53Ga0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance compared to MOSFET.

Abstract: A figure of merit I60 is proposed for sub-60 mV/decade devices as the highest current where the input characteristics exhibit a transition from sub- to super-60 mV/decade behavior. For sub-60 mV/decade devices to be competitive with metal-oxide-semiconductor field-effect devices, I60 has to be in the 1-10 μA/μm range. The best experimental tunnel field-effect transistors (TFETs) in the literature only have an I60 of 6×10-3 μA/μm but using theoretical simulations, we show that an I60 of up to 10 μA/μm should be attainable. It is proven that the Schottky barrier FET (SBFET) has a 60 mV/decade subthreshold swing limit while combining a SBFET and a TFET does improve performance.