Abstract: The last few years have seen a great deal of progress in the development of transmission electron microscopy based techniques for strain mapping. New techniques have appeared such as dark field electron holography and nanobeam diffraction and better known ones such as geometrical phase analysis have been improved by using aberration corrected ultra-stable modern electron microscopes. In this paper we apply dark field electron holography, the geometrical phase analysis of high angle annular dark field scanning transmission electron microscopy images, nanobeam diffraction and precession diffraction, all performed at the state-of-the-art to five different types of semiconductor samples. These include a simple calibration structure comprising 10-nm-thick SiGe layers to benchmark the techniques. A SiGe recessed source and drain device has been examined in order to test their capabilities on 2D structures. Devices that have been strained using a nitride stressor have been examined to test the sensitivity of the different techniques when applied to systems containing low values of deformation. To test the techniques on modern semiconductors, an electrically tested device grown on a SOI wafer has been examined. Finally a GaN/AlN superlattice was tested in order to assess the different methods of measuring deformation on specimens that do not have a perfect crystalline structure. The different deformation mapping techniques have been compared to one another and the strengths and weaknesses of each are discussed.

Abstract: Strain engineering in the conduction channel is a cost effective method of boosting the performance in state-of-the-art semiconductor devices. However, given the small dimensions of these devices, it is difficult to quantitatively measure the strain with the required spatial resolution. Three different transmission electron microscopy techniques, high-angle annular dark field scanning transmission electron microscopy, dark field electron holography, and nanobeam electron diffraction have been applied to measure the strain in simple bulk and SOI calibration specimens. These techniques are then applied to different gate length SiGe SOI pFET devices in order to measure the strain in the conduction channel. For these devices, improved spatial resolution is required, and strain maps with spatial resolutions as good as 1 nm have been achieved. Finally, we discuss the relative advantages and disadvantages of using these three different techniques when used for strain measurement.