Abstract: This paper benchmarks various epitaxial growth schemes based on n-type group-IV materials as viable source/drain candidates for Ge nMOS devices. Si:P grown at low temperature on Ge, gives an active carrier concentration as high as 3.5 x 10(20) cm(-3) and a contact resistivity down to 7.5 x 10(-9) Omega.cm(2). However, Si:P growth is highly defective due to large lattice mismatch between Si and Ge. Within the material stacks assessed, one option for Ge nMOS source/drain stressors would be to stack Si:P, deposited at contact level, on top of a selectively grown n-SiyGe1-x-ySnx at source/drain level, in line with the concept of Si passivation of n-Ge surfaces to achieve low contact resistivities as reported in literature (Martens et al. 2011 Appl. Phys. Lett., 98, 013 504). The saturation in active carrier concentration with increasing P (or As)-doping is the major bottleneck in achieving low contact resistivities for as-grown Ge or SiyGe1-x-ySnx. We focus on understanding various dopant deactivation mechanisms in P-doped Ge and Ge1-xSnx alloys. First principles simulation results suggest that P deactivation in Ge and Ge1-xSnx can be explained both by P-clustering and donor-vacancy complexes. Positron annihilation spectroscopy analysis, suggests that dopant deactivation in P-doped Ge and Ge1-xSnx is primarily due to the formation of P-n-V and SnmPn-V clusters. (C) 2020 The Author(s). Published on behalf of The Electrochemical Society by IOP Publishing Limited.