Abstract: Since the onset of pattern transfer technologies for chip manufacturing, various strategies have been developed to circumvent or overcome aspect ratio dependent etching (ARDE). These methods have, however, their own limitations in terms of etch non-idealities, throughput or costs. Moreover, they have mainly been optimized for individual in-device features and die-scale patterns, while occasionally ending up with poor patterning of metrology marks, affecting the alignment and overlay in lithography. Obtaining a better understanding of the underlying mechanisms of ARDE and how to mitigate them therefore remains a relevant challenge to date, for both marks and advanced nodes. In this work, we accordingly assessed the neutral transport mechanisms in ARDE by means of experiments and multiscale modeling for SiO₂etching with CHF₃/Ar and CF₄/Ar plasmas. The experiments revealed a local maximum in the etch rate for an aspect ratio around unity, i.e. the simultaneous occurrence of regular and inverse reactive ion etching lag for a given etch condition. We were able to reproduce this ARDE trend in the simulations without taking into account charging effects and the polymer layer thickness, suggesting shadowing and diffuse reflection of neutrals as the primary underlying mechanisms. Subsequently, we explored four methods with the simulations to regulate ARDE, by varying the incident plasma species fluxes, the amount of polymer deposition, the ion energy and angular distribution and the initial hardmask sidewall angle, for which the latter was found to be promising in particular. Although our study focusses on feature dimensions characteristic to metrology marks and back-end-of-the-line integration, the obtained insights have a broader relevance, e.g. to the patterning of advanced nodes. Additionally, this work supports the insight that physisorption may be more important in plasma etching at room temperature than originally thought, in line with other recent studies, a topic on which we recommend further research.