“Nanoscale domain wall devices with magnetic tunnel junction read and write”. Raymenants E, Bultynck O, Wan D, Devolder T, Garello K, Souriau L, Thiam A, Tsvetanova D, Canvel Y, Nikonov DE, Young IA, Heyns M, Sorée B, Asselberghs I, Radu I, Couet S, Nguyen VD, Nature Electronics 4, 392 (2021). http://doi.org/10.1038/S41928-021-00593-X
Abstract: The manipulation of fast domain wall motion in magnetic nanostructures could form the basis of novel magnetic memory and logic devices. However, current approaches for reading and writing domain walls require external magnetic fields, or are based on conventional magnetic tunnel junctions (MTJs) that are not compatible with high-speed domain wall motion. Here we report domain wall devices based on perpendicular MTJs that offer electrical read and write, and fast domain wall motion via spin-orbit torque. The devices have a hybrid free layer design that consists of platinum/cobalt (Pt/Co) or a synthetic antiferromagnet (Pt/Co/Ru/Co) into the free layer of conventional MTJs. We show that our devices can achieve good tunnelling magnetoresistance readout and efficient spin-transfer torque writing that is comparable to current magnetic random-access memory technology, as well as domain wall depinning efficiency that is similar to stand-alone materials. We also show that a domain wall conduit based on a synthetic antiferromagnet offers the potential for reliable domain wall motion and faster write speed compared with a device based on Pt/Co. Domain wall devices based on perpendicular magnetic tunnel junctions with a hybrid free layer design can offer electrical read and write, and fast domain wall motion driven via spin-orbit torque.
Keywords: A1 Journal article; Engineering sciences. Technology; Condensed Matter Theory (CMT)
DOI: 10.1038/S41928-021-00593-X
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“Reactive plasma cleaning and restoration of transition metal dichalcogenide monolayers”. Marinov D, de Marneffe J-F, Smets Q, Arutchelvan G, Bal KM, Voronina E, Rakhimova T, Mankelevich Y, El Kazzi S, Nalin Mehta A, Wyndaele P-J, Heyne MH, Zhang J, With PC, Banerjee S, Neyts EC, Asselberghs I, Lin D, De Gendt S, npj 2D Materials and Applications 5, 17 (2021). http://doi.org/10.1038/s41699-020-00197-7
Abstract: The cleaning of two-dimensional (2D) materials is an essential step in the fabrication of future devices, leveraging their unique physical, optical, and chemical properties. Part of these emerging 2D materials are transition metal dichalcogenides (TMDs). So far there is limited understanding of the cleaning of “monolayer” TMD materials. In this study, we report on the use of downstream H<sub>2</sub>plasma to clean the surface of monolayer WS<sub>2</sub>grown by MOCVD. We demonstrate that high-temperature processing is essential, allowing to maximize the removal rate of polymers and to mitigate damage caused to the WS<sub>2</sub>in the form of sulfur vacancies. We show that low temperature in situ carbonyl sulfide (OCS) soak is an efficient way to resulfurize the material, besides high-temperature H<sub>2</sub>S annealing. The cleaning processes and mechanisms elucidated in this work are tested on back-gated field-effect transistors, confirming that transport properties of WS<sub>2</sub>devices can be maintained by the combination of H<sub>2</sub>plasma cleaning and OCS restoration. The low-damage plasma cleaning based on H<sub>2</sub>and OCS is very reproducible, fast (completed in a few minutes) and uses a 300 mm industrial plasma etch system qualified for standard semiconductor pilot production. This process is, therefore, expected to enable the industrial scale-up of 2D-based devices, co-integrated with silicon technology.
Keywords: A1 Journal article; Engineering sciences. Technology; Plasma Lab for Applications in Sustainability and Medicine – Antwerp (PLASMANT)
DOI: 10.1038/s41699-020-00197-7
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“Modeling of edge scattering in graphene interconnects”. Contino A, Ciofi I, Wu X, Asselberghs I, Celano U, Wilson CJ, Tokei Z, Groeseneken G, Sorée B, IEEE electron device letters 39, 1085 (2018). http://doi.org/10.1109/LED.2018.2833633
Abstract: Graphene interconnects are being considered as a promising candidate for beyond CMOS applications, thanks to the intrinsic higher carrier mobility, lower aspect ratio and better reliability with respect to conventional Cu damascene interconnects. However, similarly to Cu, line edge roughness can seriously affect graphene resistance, something which must be taken into account when evaluating the related performance benefits. In this letter, we present a model for assessing the impact of edge scattering on the resistance of graphene interconnects. Our model allows the evaluation of the total mean free path in graphene lines as a function of graphene width, diffusive scattering probability and edge roughness standard deviation and autocorrelation length. We compare our model with other models from literature by benchmarking them using the same set of experimental data. We show that, as opposed to the considered models from literature, our model is capable to describe the mobility drop with scaling caused by significantly rough edges.
Keywords: A1 Journal article; Condensed Matter Theory (CMT)
Impact Factor: 3.048
Times cited: 1
DOI: 10.1109/LED.2018.2833633
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